Test vector ordering technique for switching activity reduction during test operation

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 24-27

  Girard, P ^a   Guiller, L ^a   Landrault, C ^a   Pravossoudovitch, S ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; FAILURE ANALYSIS; LOGIC DESIGN; SEQUENTIAL CIRCUITS; SWITCHING CIRCUITS; VECTORS; VLSI CIRCUITS;

POWER DISSIPATION; POWER RATINGS; TEST VECTOR ORDERING TECHNIQUE;

INTEGRATED CIRCUIT TESTING;

EID: 0033358302     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)