Implementation of a 3rd-generation SPARC V9 64b microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 412-413

  Heald, R ^a   Aingaran, K ^a   Amir, C ^a   Ang, M ^a   Boland, M ^a   Das, A ^a   Dixit, P ^a   Gouldsberry, G ^a   Hart, J ^a   Horel, T ^a   Hsu, W J ^a   Kaku, J ^a   Kim, C ^a   Kim, S ^a   Klass, F ^a   Kwan, H ^a   Lo, R ^a   McIntyre, H ^a   Mehta, A ^a   Murata, D ^a   Nguyen, S ^a   Pai, Y P ^a   Patel, S ^a   Shin, K ^a   Tam, K ^a   Vishwanthaiah, S ^a   Wu, J ^a   Yee, G ^a   You, H ^a   more..

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; FLIP FLOP CIRCUITS; PROGRAM PROCESSORS; STATIC RANDOM ACCESS STORAGE; TRANSISTORS;

ARCHITECTURAL REGISTER FILES (ARF); WORKING REGISTER FILES (WRF);

MICROPROCESSOR CHIPS;

EID: 0034429687     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A 64b microprocessor with multimedia support
2. A 330MHz 4-way superscalar microprocessor
3. 64KB sum-addressed-memory cache with 1.6ns cycle and 2.6ns latency
4. UltraSPARC-III: Designing third-generation 64b performance
5. A new family of semi-dynamic and dynamic flip-flops with embedded logic for high-performance processors
6. An on-chip voltage regulator using switched decoupling capacitors