Timing analysis including clock skew

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 11, 1999, Pages 1608-1618

  Harris, David ^a   Horowitz, Mark ^a  

^a HARVEY MUDD COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; FLIP FLOP CIRCUITS;

CLOCK SKEW; SAKALLAH-MUDGE-OLUKOTUN (SMO) LATCH-BASED TIMING ANALYSIS; SZYMANSKKI-SHENOY RELAXATION ALGORITHM;

TIMING CIRCUITS;

EID: 0033349678     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.806806     Document Type: Article

References (18)

1. P. Gronowski, W. Bowhill, R. Preston, M. Gowan, and R. Allmon, "High-performance microprocessor design," IEEE J. Solid-State Cir-cuits, vol. 33, pp. 676-686, May 1998.
2. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA: Addison-Wesley, 1993, p. 351.
3. A. Champernowne, L. Bushard, J. Rusterholtz, and J. Schomburg, "Latch-to-latch timing rules," IEEE Trans. Comput., vol. 39, pp. 798-808, June 1990.
4. K. Sakallah, T. Mudge, and O. Olukotun, "Analysis and design of latch-controlled synchronous digital circuits," IEEE Trans. Computer-Aided Design, vol. 11, pp. 322-333, Mar. 1992.
5. T. Szymanski and N. Shenoy, "Verifying clock schedules," in ICCAD Dig. Tech. Papers, Nov. 1992, pp. 124-131.
6. R. B. Hitchcock, "Timing verification and timing analysis program," in 25 Years of Electronic Design Automation. Piscataway, NJ: IEEE Press/ACM, 1988.
7. J. Ousterhout, "A switch-level timing verifier for digital MOS VLSI," IEEE Trans. Computer-Aided Design, vol. CAD-4, pp. 336-349, July 1985.
8. N. Jouppi, "Timing verification and performance improvement of MOS VLSI designs," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1984.
9. J. Rubinstein, P. Penfield, and M. Horowitz, "Signal delay in RC tree networks," in IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
10. S. Unger and C. Tan, "Clocking schemes for high-speed digital systems," IEEE Trans. Comput., vol. C-35, pp. 880-895, Oct 1986.
11. T. Szymanski, "LEADOUT: A static timing analyzer for MOS circuits," in ICCAD-86 Dig. Tech. Papers, 1986, pp. 130-133.
12. _, "Computing optimal clock schedules," in Proc. 29th Design Automation CoJ.,1992, pp. 399-404.
13. A. Ishii, C. Leiserson, and M. Papaefthymiou, "Optimizing two-phase, level-clocked circuitry," in J. ACM, vol. 44, no. 1, pp. 148-199, Jan. 1997.
14. T. Burks, K. Sakallah, and T. Mudge, "Critical paths in circuits with level-sensitive latches," IEEE Trans. VLSI Syst., vol. 3, no. 2, pp. 273-291, June 1995.
15. P. Gronowski et al., "A 433-MHz 64-b quad-issue RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, pp. 1687-1696, Nov. 1996.
16. K. Venkat, L. Chen, I. Lin, P. Mistry, and P. Madhani, "Timing verification of dynamic circuits," IEEE J. Solid-State Circuits, vol. 31, pp. 452-455, Mar. 1996.
17. D. Van Campenhout, T. Mudge, and K. Sakallah, "Timing verification of sequential domino circuits," in ICC AD-96 Dig. Tech. Papers, 1996.
18. J. Kuskin et al, "The Stanford FLASH multiprocessor," in Proc. Int. Symp. Comp. Arch., Apr. 1994, pp. 302-313.