A 64-b quad-issue CMOS RISC microprocessor

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1697-1702

  Gaddis, Neela ^a,c   Lotz, Jonathan ^a,b,d  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c STANFORD UNIVERSITY   (United States)

^d PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; LOGIC CIRCUITS; REDUCED INSTRUCTION SET COMPUTING; TIMING CIRCUITS; TRANSISTORS; VLSI CIRCUITS;

CLOCK CIRCUITS; DYNAMIC LOGIC; INSTRUCTION REORDER BUFFER;

MICROPROCESSOR CHIPS;

EID: 0030284682     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.1996.542314     Document Type: Article

References (8)

1. J. Lotz et al., "A quad-issue out-of-order RISC CPU," in Dig. Papers, ISSCC-96, Feb. 1996, pp. 210-211.
2. N. Gaddis et al., "A 56 entry instruction reorder buffer," in Dig. Papers, ISSCC-96, Feb. 1996, pp. 212-213.
3. D. Hunt, "Advanced performance features of the 64-bit PA-8000," in Dig. Papers, Compcon, Mar. 1995, pp. 123-128.
4. R. Naas, "Memory performance features of the 64-bit PA-8000," presented at Symp. Rec., Hot chips VII, Aug. 1995.
5. G. Kane, PA-RISC 2.0 Architecture. Englewood Cliffs, NJ: Prentice-Hall, 1996.
6. S. Naffziger, "A subnanosecond 0.5 mm 64 b adder design," in Dig. Papers, ISSCC-96, Feb. 1996, pp. 362-363.
7. G. Colon-Bonet et al, "A dual floating point coprocessor with an FMAC architecture," in Dig. Papers, ISSCC-96, Feb. 1996, pp. 354-355.
8. http://www.specbench.org/osg/cpu95/results/.