Analysis of the impact of process variations on clock skew

IEEE Transactions on Semiconductor Manufacturing

Volumn 13, Issue 4, 2000, Pages 401-407

  Zanella, Stefano ^a,b   Nardi, Alessandra ^a,b   Neviani, Andrea ^a,b   Quarantelli, Michele ^a,c   Saxena, Sharad ^a,d   Guardiani, Carlo ^a,e  

^a IEEE

^b UNIVERSITY OF PADOVA   (Italy)

^c UNIVERSITY OF BRESCIA   (Italy)

^d PDF Solutions   (United States)

^e PDF SOLUTIONS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC NETWORK PARAMETERS; MONTE CARLO METHODS; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCK DISTRIBUTION NETWORKS; CLOCK SKEW; MANUFACTURABILITY; PROCESS VARIATIONS; TIMING ANALYSIS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0034313367     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/66.892625     Document Type: Article

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