Low power BIST design by hypergraph partitioning: methodology and architectures

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 652-661

  Girard, P ^a   Guiller, L ^a   Landrault, C ^a   Pravossoudovitch, S ^a  

^a UNIV MONTPELLIER   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; ITERATIVE METHODS;

HYPERGRAPH PARTITIONING; SOFTWARE PACKAGE HSPICE;

BUILT-IN SELF TEST;

EID: 0034476102     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (35)