Testing interconnects for noise and skew in gigahertz SoCs

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 305-314

  Attarha, Amir ^a   Nourani, Mehrdad ^a  

^a UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; CROSSTALK; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

SYSTEM-ON-CHIP (SOC); VOLTAGE DISTORTION;

INTERCONNECTION NETWORKS;

EID: 0035683903     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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