Dealing with inductance in high-speed chip design

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 904-909

  Restle, Phillip ^a   Ruehli, Albert ^a   Walker, Steven G ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC NETWORK SYNTHESIS; EQUIVALENT CIRCUITS; INDUCTANCE MEASUREMENT; MICROPROCESSOR CHIPS;

PARTIAL ELEMENT EQUIVALENT CIRCUIT (PEEC);

INTERCONNECTION NETWORKS;

EID: 0032643292     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.310096     Document Type: Conference Paper

References (9)