메뉴 건너뛰기




Volumn 41, Issue 4-5, 1997, Pages 611-626

Advanced microprocessor test strategy and methodology

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTER SOFTWARE; MICROPROCESSOR CHIPS;

EID: 0031177245     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.414.0611     Document Type: Article
Times cited : (26)

References (37)
  • 1
    • 0015385079 scopus 로고
    • A New Representation for Faults in Combinational Digital Circuits
    • August
    • D. R. Schertz and G. Metze, "A New Representation for Faults in Combinational Digital Circuits," IEEE Trans. Computers C-21, 858-866 (August 1972).
    • (1972) IEEE Trans. Computers , vol.C-21 , pp. 858-866
    • Schertz, D.R.1    Metze, G.2
  • 2
    • 3643082222 scopus 로고    scopus 로고
    • "Method of Level Sensitive Testing a Functional Logic System," U.S. Patent 3,761,695, September 25, 1973
    • E. B. Eichelberger, "Method of Level Sensitive Testing a Functional Logic System," U.S. Patent 3,761,695, September 25, 1973.
    • Eichelberger, E.B.1
  • 5
    • 3643112399 scopus 로고    scopus 로고
    • "Level-Sensitive Scan Design System," U.S. Patent 4,293,919, October 6, 1981
    • S. DasGupta, P. Goel, and T. W. Williams, "Level-Sensitive Scan Design System," U.S. Patent 4,293,919, October 6, 1981.
    • DasGupta, S.1    Goel, P.2    Williams, T.W.3
  • 7
    • 0019930896 scopus 로고
    • Processor Controller for the IBM 3081
    • January
    • John Reilly, Arthur Sutton, Robert Nasser, and Robert Griscom, "Processor Controller for the IBM 3081," IBM J. Res. Develop. 26, No. 1, 22-29 (January 1982).
    • (1982) IBM J. Res. Develop. , vol.26 , Issue.1 , pp. 22-29
    • Reilly, J.1    Sutton, A.2    Nasser, R.3    Griscom, R.4
  • 8
    • 0025232232 scopus 로고
    • Pseudorandom Built-In Self-Test Methodology and Implementation for the IBM RISC System/6000 Processor
    • January
    • I. M. Ratiu and H. B. Bakoglu, "Pseudorandom Built-In Self-Test Methodology and Implementation for the IBM RISC System/6000 Processor," IBM J. Res. Develop. 34, No. 1, 78-84 (January 1990).
    • (1990) IBM J. Res. Develop. , vol.34 , Issue.1 , pp. 78-84
    • Ratiu, I.M.1    Bakoglu, H.B.2
  • 9
    • 0025403183 scopus 로고
    • Design for Testability and Diagnosis in a VLSI CMOS System/370 Processor
    • March/May
    • Cordt W. Starke, "Design for Testability and Diagnosis in a VLSI CMOS System/370 Processor." IBM J. Res. Develop. 34, No. 2/3, 355-362 (March/May 1990).
    • (1990) IBM J. Res. Develop. , vol.34 , Issue.2-3 , pp. 355-362
    • Starke, C.W.1
  • 10
    • 0025401456 scopus 로고
    • Self-Testing the 16-Mbps Adapter Chip for the IBM Token-Ring Local Area Network
    • March/May
    • S. F. Oakland, J. L. Corr, J. D. Blair, R. D. Norman, and W. J. DeGuise, "Self-Testing the 16-Mbps Adapter Chip for the IBM Token-Ring Local Area Network," IBM J. Res. Develop. 34, No. 2/3, 416-427 (March/May 1990).
    • (1990) IBM J. Res. Develop. , vol.34 , Issue.2-3 , pp. 416-427
    • Oakland, S.F.1    Corr, J.L.2    Blair, J.D.3    Norman, R.D.4    DeGuise, W.J.5
  • 13
    • 0030196870 scopus 로고    scopus 로고
    • Test Methodologies and Design Automation for IBM ASICs
    • July
    • P. Gillis, T. Guzowski, B. Keller, and R. Kerr, "Test Methodologies and Design Automation for IBM ASICs," IBM J. Res. Develop. 40, No. 4, 461-474 (July 1996).
    • (1996) IBM J. Res. Develop. , vol.40 , Issue.4 , pp. 461-474
    • Gillis, P.1    Guzowski, T.2    Keller, B.3    Kerr, R.4
  • 14
    • 0019543877 scopus 로고
    • An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
    • March
    • P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Trans. Computers C-30, 215-222 (March 1981).
    • (1981) IEEE Trans. Computers , vol.C-30 , pp. 215-222
    • Goel, P.1
  • 15
    • 3643097779 scopus 로고    scopus 로고
    • "Weighted Random Pattern Testing Apparatus and Method," U.S. Patent 4,688,233, August 18, 1987
    • F. Motika and J. Waicukauski, "Weighted Random Pattern Testing Apparatus and Method," U.S. Patent 4,688,233, August 18, 1987.
    • Motika, F.1    Waicukauski, J.2
  • 19
    • 0025404497 scopus 로고
    • Built-In Self-Test Support in the IBM Engineering Design System
    • March/May
    • B. L. Keller and T. J. Snethen, "Built-In Self-Test Support in the IBM Engineering Design System," IBM J. Res. Develop. 34, No. 2/3, 406-415 (March/May 1990).
    • (1990) IBM J. Res. Develop. , vol.34 , Issue.2-3 , pp. 406-415
    • Keller, B.L.1    Snethen, T.J.2
  • 21
    • 0020496768 scopus 로고
    • Design for Testability - A Survey
    • January
    • T. W. Williams and K. P. Parker, "Design for Testability - A Survey," Proc. IEEE 31, No. 1, 18-22 (January 1983).
    • (1983) Proc. IEEE , vol.31 , Issue.1 , pp. 18-22
    • Williams, T.W.1    Parker, K.P.2
  • 22
    • 0021521542 scopus 로고
    • LOCST: A Built-In Self-Test Technique
    • November
    • J. J. LeBlanc, "LOCST: A Built-In Self-Test Technique," IEEE Design and Test, pp. 45-52 (November 1984).
    • (1984) IEEE Design and Test , pp. 45-52
    • LeBlanc, J.J.1
  • 28
    • 0003415191 scopus 로고
    • IEEE Standard 1149.1-1990, IEEE Standards Board, 345 East 47th Street, New York, NY 10017
    • IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1-1990, IEEE Standards Board, 345 East 47th Street, New York, NY 10017, 1990.
    • (1990) IEEE Standard Test Access Port and Boundary-Scan Architecture
  • 29
    • 3643109270 scopus 로고    scopus 로고
    • "Programmable Clock Tuning System and Method," U.S. Patent 5,455,931, October 3, 1995
    • P. J. Camporese, P. J. Meaney, B. J. O'Leary, and R. R. Rizzolo, "Programmable Clock Tuning System and Method," U.S. Patent 5,455,931, October 3, 1995.
    • Camporese, P.J.1    Meaney, P.J.2    O'Leary, B.J.3    Rizzolo, R.R.4
  • 30
    • 3643065473 scopus 로고
    • Off-Chip Module Clock Controller
    • September
    • A. M. Cady and G. A. Hughes, "Off-Chip Module Clock Controller," IBM Tech. Disclosure Bull. 32, No. 4A, 77-78 (September 1989).
    • (1989) IBM Tech. Disclosure Bull. , vol.32 , Issue.4 A , pp. 77-78
    • Cady, A.M.1    Hughes, G.A.2
  • 33
    • 3643144702 scopus 로고    scopus 로고
    • "Programmable Computer System Element with Built-In Self Test Method and Apparatus for Repair During Power-On," U.S. Patent 5,659,551, May 1966
    • W. Huott, T. J. Siegel, T. Lo, and P. Patel, "Programmable Computer System Element with Built-In Self Test Method and Apparatus for Repair During Power-On," U.S. Patent 5,659,551, May 1966.
    • Huott, W.1    Siegel, T.J.2    Lo, T.3    Patel, P.4
  • 34
    • 3643074942 scopus 로고    scopus 로고
    • "Programmable Delay Clock Chopper/Stretcher With Fast Recovery," U.S. Patent 5,420,467, February 2, 1996
    • W. Huott and T. McNamara, "Programmable Delay Clock Chopper/Stretcher With Fast Recovery," U.S. Patent 5,420,467, February 2, 1996.
    • Huott, W.1    McNamara, T.2
  • 36
    • 0029219688 scopus 로고
    • Verity - A Formal Verification Program for Custom CMOS Circuits
    • January/March
    • A. Kuehlmann, A. Srinivasan, and D. P. LaPotin, "Verity - A Formal Verification Program for Custom CMOS Circuits," IBM J. Res. Develop. 39, No. 1/2, 149-165 (January/March 1995).
    • (1995) IBM J. Res. Develop. , vol.39 , Issue.1-2 , pp. 149-165
    • Kuehlmann, A.1    Srinivasan, A.2    LaPotin, D.P.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.