Exploring the limits of gate dielectric scaling

Semiconductor International

Volumn 24, Issue 6, 2001, Pages 153-158

  Wallace, R M ^a   Wilk, G D ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIELECTRIC FILMS; LOGIC DEVICES; PERMITTIVITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SUBSTRATES; THRESHOLD VOLTAGE;

GATE DIELECTRICS;

GATES (TRANSISTOR);

EID: 0035360029     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (22)

1. Generalized scaling theory and its application to a 1/4 micron MOSFET design
2. 30nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
3. Determination of ultra-thin gate oxide thicknesses for CMOS structures using quantum effects
4. The ballistic nano-transistor
5. Gate oxides in 50nm devices: Thickness uniformity improves projected reliability
6. Limits of gate-oxide scaling in nano-transistors
7. The electronic structure at the atomic scale of ultrathin gate oxides
8. Evaluating the minimum thickness of gate oxide on silicon using first-principals methods
9. Reliability projection for ultra-thin oxides at low voltage
10. Ultimate limit for defect generation in ultra-thin silicon dioxide
11. Boron diffusion and penetration in ultrathin oxide with poly-Si gate
12. Ultrathin nitrogen-profile engineered gate dielectric films
13. +/- polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced CVD/thermal oxidation process
14. Design of sub-100nm CMOSFETs: Gate dielectrics and channel engineering
15. 2 technology
16. High-k gate dielectrics: Current status and materials properties considerations