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Volumn 41, Issue 4, 2001, Pages 587-595

Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CHEMICAL VAPOR DEPOSITION; DIELECTRIC MATERIALS; INTERFACES (MATERIALS); SEMICONDUCTING SILICON COMPOUNDS; STOICHIOMETRY; STRESS ANALYSIS; X RAY PHOTOELECTRON SPECTROSCOPY;

EID: 0035310399     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(00)00247-X     Document Type: Article
Times cited : (17)

References (16)
  • 1
    • 0032284170 scopus 로고    scopus 로고
    • Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs
    • (1998) IEDM Tech Dig , pp. 747-750
    • Liu, C.T.1
  • 2
    • 0005215678 scopus 로고    scopus 로고
    • SEMATECH, International technology roadmap for the semiconductors
    • (1999)
  • 5
    • 0033332092 scopus 로고    scopus 로고
    • Integration of ultrathin (1.6 ∼ 2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs
    • (1999) IEDM Tech Dig , pp. 245-248
    • Yang, H.1    Lucovsky, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.