Path delay fault diagnosis and coverage - a metric and an estimation technique

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 3, 2001, Pages 440-457

  Sivaraman, Mukund ^a,b,c   Strojwas, Andrzej J ^a,d  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c HEWLETT PACKARD LABORATORIES   (United States)

^d CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Delay effects; Delay fault testing; Fault coverage; Fault diagnosis; Path delay faults

Indexed keywords

DELAY EFFECTS; DELAY FAULT TESTING; FAULT COVERAGE; FAULT DIAGNOSIS; PATH DELAY FAULTS; STATISTICAL DIAGNOSIS;

COMPUTER SIMULATION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MAXIMUM LIKELIHOOD ESTIMATION; PERTURBATION TECHNIQUES; PROBABILITY DISTRIBUTIONS; STATISTICAL METHODS; VECTORS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035273034     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.913761     Document Type: Article

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