Efficient diagnosis of path delay faults in digital logic circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 471-475

  Pant, Pankai ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN FOR TESTABILITY; ERROR ANALYSIS; LOGIC DESIGN;

DIGITAL LOGIC CIRCUITS; EFFECT CAUSE ANALYSIS; PATH DELAY FAULTS; ROBUSTLY TESTED PATH DELAY FAULTS;

LOGIC CIRCUITS;

EID: 0033326101     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)