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Volumn , Issue , 2001, Pages 194-199

Squaring the FIFO in GasP

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS CIRCUITS; DESIGN METHOD; GASP CIRCUITS; GRAPHICAL NOTATION; HIGH-THROUGHPUT; LOW LATENCY; MAXIMUM THROUGHPUT; NOVEL DESIGN; TEST CHIPS; TIME SEPARATION;

EID: 77957936247     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2001.914083     Document Type: Conference Paper
Times cited : (34)

References (6)
  • 2
    • 67649550291 scopus 로고
    • Low latency self-timed flow-through FIFOs
    • W.J. Dally, J.W. Poulton, and A.T. Ishii (eds)
    • Low Latency Self-Timed Flow-Through FIFOs, Erik Brunvand, Advanced Research in VLSI, W.J. Dally, J.W. Poulton, and A.T. Ishii (eds), pp. 76-90, 1995.
    • (1995) Advanced Research in VLSI , pp. 76-90
    • Brunvand, E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.