Hierarchical ATPG for analog circuits and systems

IEEE Design and Test of Computers

Volumn 18, Issue 1, 2001, Pages 72-81

  Soma, Main ^a,e   Huynh, Sam ^b,c   Zhang, Jinyan ^d   Kim, Seongwon ^e   Devarayanadurg, Giri ^a,f  

^a UNIVERSITY OF WASHINGTON   (United States)

^b ATI Research Silicon Valley   (United States)

^c IEEE   (Japan)

^d ALTERA CORPORATION   (United States)

^e University of Washington   (United States)

^f INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATION; FIGURE OF MERIT; INVERSE TRANSFORM; PATH SENSITIZATION ALGORITHMS; SOFTWARE PACKAGE SPICE; TESTABILITY TRANSFER FACTOR;

ALGORITHMS; CALCULATIONS; COMPUTER SIMULATION; MATHEMATICAL TRANSFORMATIONS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; TRANSFER FUNCTIONS;

INTEGRATED CIRCUIT TESTING;

EID: 0035119967     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.902824     Document Type: Article

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