Hierarchical test generation for analog circuits using incremental test development

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 296-301

  Voorakaranam, Ramakrishna ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONTROLLABILITY; EMBEDDED SYSTEMS; LINEAR INTEGRATED CIRCUITS; OBSERVABILITY; OPTIMIZATION; WAVEFORM ANALYSIS;

ANALOG CIRCUITS; EMBEDDED MODULES; HIERARCHICAL TEST GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0032639197     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (12)