Efficient test generation for transient testing of analog circuits using partial numerical simulation

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1999, Pages 214-219

  Variyam, Pramodchandran N ^a   Hou, Junwei ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; HEURISTIC METHODS; ITERATIVE METHODS; LINEAR INTEGRATED CIRCUITS; OPTIMIZATION;

ANALOG CIRCUITS; SEARCH BASED TEST GENERATION STRATEGY;

INTEGRATED CIRCUIT TESTING;

EID: 0032678905     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (24)