Effects of microvia build-up layers on the solder joint reliability of a wafer level chip scale package (WLCSP)

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2001, Pages 1207-1215

  Lau, J H ^a   Ricky Lee, S W ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CREEP; ELASTICITY; ELASTOPLASTICITY; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT TESTING; PRINTED CIRCUIT BOARDS; SOLDERED JOINTS; STRAIN; STRESSES; THERMAL CYCLING; WSI CIRCUITS;

FINITE ELEMENT MESH; GARAFALO ARRHENIUS CREEP CONSTITUTIVE EQUATION; MICROVIA BUILD UP LAYERS; WAFEL LEVEL CHIP SCALE PACKAGES; WAFER LEVEL REDISTRIBUTION;

CHIP SCALE PACKAGES;

EID: 0034823080     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2001.927982     Document Type: Article

References (29)

1. Wafer level chip scale packaging (WL-CSP): An overview
2. A manufacturing perspective of wafer level CSP
3. Fab integrated packaging (FIP): A new concept for high reliability wafer-level chip size packaging
4. Optimal structure of wafer level package for the electrical performance
5. One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications
6. 3)
7. Wafer level CSP using low cost electroless redistribution layer
8. Recent advances on a wafer-level flip chip packaging process
9. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
10. Nonlinear fracture mechanics analysis of wafer-level chip scale package solder joints with cracks
11. A novel and reliable wafer-level chip scale package (WLCSP)
12. Fabrication of wafer level chip scale packaging for optoelectronic devices
13. Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis
14. Creep analysis of wafer level chip scale package (WLCSP) with 96.5Sn-3.5Ag and 100In lead-free solder joints and microvia build-up printed circuit board
15. Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability
16. A new thermal-fatigue life prediction model for wafer level chip scale package (WLCSP) solder joints
17. Overview of microvia technologies
18. Nonlinear-time-dependent analysis of micro via-in-pad substrates for solder bumped flip chip applications
19. Elastic, elastic-plastic, and creep analyses of wafer level chip scale package solder joints on microvia build-up printed circuit boards
20. Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints
21. Constitutive relations for tin-based solder joints