Wafer level CSP using low cost electroless redistribution layer

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 107-113

  Teutsch, Thorsten ^a   Oppert, Thomas ^a   Zakel, Elke ^a   Klusmann, Eckart ^b   Meyer, Heinrich ^b   Schulz, Ralf ^b   Schulze, Joerg ^b  

^a Pac Tech Packaging Technologies GmbH   (Germany)

^b ATOTECH DEUTSCHLAND GMBH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; DEFECTS; ELECTROLESS PLATING; METALLIZING; NICKEL ALLOYS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; PRINTED CIRCUIT BOARDS; SILICON WAFERS; SOLDERING;

COST BUMPING TECHNIQUES; ELECTROLESS COPPER CIRCUITIZATION; UNDER BUMP METALLIZATION; WAFER LEVEL CHIP SCALE PACKAGE;

CHIP SCALE PACKAGES;

EID: 0034476468     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)