Optimal structure of wafer level package for the electrical performance

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2000, Pages 530-534

  Ahn, Mee Hyun ^a   Lee, Dong ho ^a   Kang, Sa Yoon ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; DIELECTRIC MATERIALS; ELECTRIC PROPERTIES; RELIABILITY;

ELECTROMAGNETIC SIMULATION; WAFER LEVEL PACKAGE;

ELECTRONICS PACKAGING;

EID: 0034476407     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)