Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn , Issue , 2000, Pages 33-46

  Lau, J H ^a  

^a Express Packaging Systems Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; CHIP SCALE PACKAGES; COMPUTER SIMULATION; COST BENEFIT ANALYSIS; FINITE ELEMENT METHOD; PRINTED CIRCUIT BOARDS; RELIABILITY; SILICON WAFERS; SOLDERED JOINTS;

SOFTWARE PACKAGE ANSYS; WAFER LEVEL CHIP SCALE PACKAGES;

ELECTRONICS PACKAGING;

EID: 0034448401     PISSN: 10898190     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (23)

1. Wafer level chip scale packaging (WL-CSP): An overview
2. A manufacturing perspective of wafer level CSP
3. Fab integrated packaging (FIP): A new concept for high reliability wafer-level chip size packaging
4. Optimal structure of wafer level package for the electrical performance
5. One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications
6. 3)
7. Wafer level CSP using low cost electroless redistribution layer
8. Recent advances on a wafer-level flip chip packaging process
9. Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies
10. Nonlinear fracture mechanics analysis of wafer-level chip scale package solder joints with cracks
11. A novel and reliable wafer-level chip scale package (WLCSP)
12. Fabrication of wafer level chip scale packaging for optoelectronic devices
13. Solder joint reliability of wafer level chip scale packages (WLCSP): A time-temperature-dependent creep analysis
14. Cost analysis: Solder bumped flip chip versus wire bonding
15. Overview of microvia technologies
16. Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints