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Volumn 2000-AG, Issue , 2000, Pages 91-101

A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELASTOPLASTICITY; FINITE ELEMENT METHOD; FRACTURE MECHANICS; PRINTED CIRCUIT BOARDS; STRAIN ENERGY;

EID: 85120431836     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE2000-2259     Document Type: Conference Paper
Times cited : (5)

References (16)
  • 3
    • 0033687377 scopus 로고    scopus 로고
    • Wafer Level Chip Scale Packaging (WL-CSP): An Overview
    • (3) May
    • (3) Garrou, P., "Wafer Level Chip Scale Packaging (WL-CSP): An Overview", IEEE Transactions on Advanced Packaging, Vol. 23, No. 2, May 2000, pp. 198-205.
    • (2000) IEEE Transactions on Advanced Packaging , vol.23 , Issue.2 , pp. 198-205
    • Garrou, P.1
  • 7
    • 0034484432 scopus 로고    scopus 로고
    • One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications
    • (7) May
    • (7) Mirza, A. R., "One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 676-680.
    • (2000) IEEE Proceedings of Electronic Components & Technology Conference , pp. 676-680
    • Mirza, A. R.1
  • 8
    • 0034479488 scopus 로고    scopus 로고
    • Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S3)
    • (8) May
    • (8) Simon, J., and H. Reichl, "Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S3)", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 81-86.
    • (2000) IEEE Proceedings of Electronic Components & Technology Conference , pp. 81-86
    • Simon, J.1    Reichl, H.2
  • 11
    • 0034476691 scopus 로고    scopus 로고
    • Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies
    • (ll), May
    • (ll)Lau, J. H., C. Chang, and S. W. Lee, "Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 1360-1368.
    • (2000) IEEE Proceedings of Electronic Components & Technology Conference , pp. 1360-1368
    • Lau, J. H.1    Chang, C.2    Lee, S. W.3
  • 12
    • 0002185290 scopus 로고    scopus 로고
    • Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks
    • (12), September
    • (12)Lau, J. H., S. Pan, and C. Chang, "Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks", Proceedings of IMAPS 2000 Microelectronics Conference, September 2000.
    • (2000) Proceedings of IMAPS 2000 Microelectronics Conference
    • Lau, J. H.1    Pan, S.2    Chang, C.3
  • 16
    • 0003912676 scopus 로고    scopus 로고
    • (16), Revision 5.6.1
    • (16)ANSYS User's Manual, Revision 5.6.1,2000.
    • (2000) ANSYS User's Manual


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.