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(2) McGraw-Hill, New York, NY
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(2) Lau, J. H., and S. W. Lee, Chip Scale Package: Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, NY, 1999.
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(5) Topper, M., J. Auersperg, V. Glaw, K. Kaskoun, E. Prack, B. Keser, P. Coskina, D. Jager, D. Petter, O. Ehrmann, K. Samulewicz, C. Meinherz, S. Fehlberg, C. Karduck, and H. Reichl, "Fab Integrated Packaging (FTP): A New Concept for High Reliability Wafer-Level Chip Size Packaging", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 74-80.
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(6) Ann, M., D. Lee, and S. Kang, "Optimal Structure of Wafer Level Package for the Electrical Performance", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 530-534.
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(7) Mirza, A. R., "One Micron Precision, Wafer-Level Aligned Bonding for Interconnect, MEMS and Packaging Applications", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 676-680.
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(8) Simon, J., and H. Reichl, "Board Level Reliability of a Waferlevel CSP using Stacked Solder Spheres and a Solder Support Structure (S3)", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 81-86.
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Simon, J.1
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Wafer Level CSP using Low Cost Electroless Redistribution Layer
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(9) May
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(9) Teutsch, T., T. Oppert, E. Zakel, E. Klusmann, H. Meyer, R. Schulz, and J. Schulze, "Wafer Level CSP using Low Cost Electroless Redistribution Layer", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 107-113.
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IEEE Proceedings of Electronic Components & Technology Conference
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Teutsch, T.1
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10
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(10), May
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(10)Tong, Q., B. Ma, E. Zhang, A. Savoca, L. Nguyen, C. Quentin, S. Luo, H. Li, L. Fan, and C. P. Wong, "Recent Advances on a Wafer-Level Flip Chip Packaging Process", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 101-106.
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Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies
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(ll), May
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(ll)Lau, J. H., C. Chang, and S. W. Lee, "Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies", IEEE Proceedings of Electronic Components & Technology Conference, May 2000, pp. 1360-1368.
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Lau, J. H.1
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Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks
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(12), September
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(12)Lau, J. H., S. Pan, and C. Chang, "Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks", Proceedings of IMAPS 2000 Microelectronics Conference, September 2000.
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Lau, J. H.1
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A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP)
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(13), SEMI, September
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(13)Lau, J. H., T. Chung, S. W. Lee, C. Chang, and C. Chen, "A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP)", Proceedings of the Chip Scale International, SEMI, September 1999, pp. H 1-8.
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Proceedings of the Chip Scale International
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14
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Fabrication of Wafer Level Chip Scale Packaging for Optoelectronic Devices
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(14) June
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(14) Jim, K. L., G. Faulkner, D. O'Brien, D. Edwards, and J. H. Lau, "Fabrication of Wafer Level Chip Scale Packaging for Optoelectronic Devices", IEEE Proceedings of Electronic Components & Technology Conference, June 1999, pp. 1145-1147.
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15
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Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis
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(15), November
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(15)Lau, J. H., S. W. Lee, C. Chang, and C. Chen, "Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis", ASME Paper No. 99-IMECE/EEP-5, International Mechanical Engineering Congress and Exposition, November 1999.
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Lau, J. H.1
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