-
3
-
-
84945714736
-
-
141-149, Feb. 1985.
-
M. E. Alperin etal., "Development of the self-aligned titanum suicide process for VLSI applications," IEEE Trans. Electron. Devices, vol. ED-32, pp. 141-149, Feb. 1985.
-
"Development of the Self-aligned Titanum Suicide Process for VLSI Applications," IEEE Trans. Electron. Devices, Vol. ED-32, Pp.
-
-
Alperin, M.E.1
-
4
-
-
0027889412
-
-
0.1 //m-CMOS at room temperature using high performance Co salicide process," in IEDM Tech. Dig., 1993, pp. 906-907.
-
T. Yamazaki et al., "21 psc switching 0.1 //m-CMOS at room temperature using high performance Co salicide process," in IEDM Tech. Dig., 1993, pp. 906-907.
-
"21 Psc Switching
-
-
Yamazaki, T.1
-
5
-
-
0029715056
-
-
0.15 /j,m single gate Co salicide CMOS," in Symp. VLSI Tech. Dig., 1996, pp. 34-35.
-
T. Yoshitomi et al., "High performance 0.15 /j,m single gate Co salicide CMOS," in Symp. VLSI Tech. Dig., 1996, pp. 34-35.
-
"High Performance
-
-
Yoshitomi, T.1
-
6
-
-
33749897906
-
-
97-3, pp. 275-295, 1997.
-
T. Ohguro et al, "Ultra-shallow junction and salicide techniques for advanced CMOS devices," Proc. Electrochem. Soc., vol. 97-3, pp. 275-295, 1997.
-
"Ultra-shallow Junction and Salicide Techniques for Advanced CMOS Devices," Proc. Electrochem. Soc., Vol.
-
-
Ohguro, T.1
-
7
-
-
0029717430
-
-
2 GHz operation," in Symp. VLSI Tech. Dig., 1997, pp. 132-133.
-
T. Ohguro, E. Morifuji, Msaito, M. Ono, T. Yoshitomi, H. S. Momose, N. Ito, and H. Iwai, "0.2 /j,m analog CMOS with very low noise figure at 2 GHz operation," in Symp. VLSI Tech. Dig., 1997, pp. 132-133.
-
E. Morifuji, Msaito, M. Ono, T. Yoshitomi, H. S. Momose, N. Ito, and H. Iwai, "0.2 /J,m Analog CMOS with Very Low Noise Figure at
-
-
Ohguro, T.1
-
8
-
-
0030704850
-
-
pp. 13-14.
-
T. C. Holloway et ai, "0.18 //m CMOS technology for high-performance, low-power, and RF applications," in Symp. VLSI Tech. Dig., 1997, pp. 13-14.
-
0.18 //M CMOS Technology for High-performance, Low-power, and RF Applications," in Symp. VLSI Tech. Dig., 1997
-
-
Holloway, T.C.1
-
10
-
-
0030689148
-
-
1997, pp. 23-24.
-
M. Tsukamoto, H. Kuroda, and Y Okamoto, "0.25 ftm W-polycide dual gate and buried metal on diffusion layer (BMD) technology for DRAMEmbedded logic devices," in Symp. VLSI Tech. Dig., 1997, pp. 23-24.
-
H. Kuroda, and y Okamoto, "0.25 Ftm W-polycide Dual Gate and Buried Metal on Diffusion Layer (BMD) Technology for DRAMEmbedded Logic Devices," in Symp. VLSI Tech. Dig.
-
-
Tsukamoto, M.1
-
12
-
-
0025474417
-
-
37, pp. 1842-1851, Aug. 1990.
-
J. R. Pfiester et al., "The effects of boron penetration on P+ polysilicon gated PMOS devices," IEEE Trans. Electron. Devices, vol. 37, pp. 1842-1851, Aug. 1990.
-
"The Effects of Boron Penetration on P+ Polysilicon Gated PMOS Devices," IEEE Trans. Electron. Devices, Vol.
-
-
Pfiester, J.R.1
-
13
-
-
0030679335
-
-
1997, pp. 89-90.
-
S. Shishiguchi, A. Mineji, T. Hayashi, and S. Saito, "Boron implanted shallow junction formation by high-temperature/short-time/highram (400C/sec) RTA," in Symp. VLSI Tech. Dig., 1997, pp. 89-90.
-
A. Mineji, T. Hayashi, and S. Saito, "Boron Implanted Shallow Junction Formation by High-temperature/short-time/highramping-rate (400°C/sec) RTA," in Symp. VLSI Tech. Dig.
-
-
Shishiguchi, S.1
-
14
-
-
0026105523
-
-
38, pp. 262-269, Feb. 1991.
-
J. B. Lasky, J. S. Nakos, O. J. Cain, and P. J. Geiss, "Comparison of transformation to low-resistivity phase and agglomeration of TiSi2 and CoSi2," IEEE Trans. Electron. Devices, vol. 38, pp. 262-269, Feb. 1991.
-
J. S. Nakos, O. J. Cain, and P. J. Geiss, "Comparison of Transformation to Low-resistivity Phase and Agglomeration of TiSi2 and CoSi2," IEEE Trans. Electron. Devices, Vol.
-
-
Lasky, J.B.1
-
15
-
-
33749925232
-
-
1996, pp. 395-397.
-
H. Minakata, K. Goto, and T. Sugii, "Effect of cap-metal on Co salicide process," in Ext. Abst. Int. Conf. Solid State Devices and Materials, Yokohama, 1996, pp. 395-397.
-
K. Goto, and T. Sugii, "Effect of Cap-metal on Co Salicide Process," in Ext. Abst. Int. Conf. Solid State Devices and Materials, Yokohama
-
-
Minakata, H.1
-
17
-
-
33749927034
-
-
1994, pp. 640-642.
-
J. S. Byun, C. R. Kirn, K. G. Rha, J. J. Kirn, and W. S. Kirn, "TiN/TiSi2 formation using TiNx layer and its feasibilities in ULSI," in Ext. Abst. Int. Conf. Solid State Devices and Materials, Yokohama, 1994, pp. 640-642.
-
C. R. Kirn, K. G. Rha, J. J. Kirn, and W. S. Kirn, "TiN/TiSi2 Formation Using TiNx Layer and Its Feasibilities in ULSI," in Ext. Abst. Int. Conf. Solid State Devices and Materials, Yokohama
-
-
Byun, J.S.1
-
19
-
-
0028743070
-
-
32, pp. 2305-2317, Dec. 1994.
-
T. Ohguro et al., "Analysis of resistance behavior in Ti- and Ni-Saliicded polysilicon films," IEEE Trans. Electron. Devices, vol. 32, pp. 2305-2317, Dec. 1994.
-
"Analysis of Resistance Behavior in Ti- and Ni-Saliicded Polysilicon Films," IEEE Trans. Electron. Devices, Vol.
-
-
Ohguro, T.1
|