0.25 μm W-polycide dual gate and buried metal on diffusion layer (BMD) technology for DRAM-embedded logic devices

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 23-24

  Tsukamoto, M ^a   Kuroda, H ^a   Okamoto, Y ^a  

^a SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; DIFFUSION IN SOLIDS; GATES (TRANSISTOR); LOGIC DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SEMICONDUCTOR GROWTH; SEMICONDUCTOR STORAGE;

BURIED METAL ON DIFFUSION LAYER (BMD) TECHNOLOGY; DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0030689148     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)