21 psec switching 0.1μm-CMOS at room temperature using high performance Co salicide process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 906-908

  Yamazaki, Tatsuya ^a   Goto, Kenichi ^a   Fukano, Tbtsu ^a   Nara, Yasuo ^a   Sugii, Ibshihiro ^a   Ito, Takashi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

SILICIDES; COBALT; DOPING (ADDITIVES); GATES (TRANSISTOR); MOS DEVICES; SWITCHING CIRCUITS;

CAPPING PROCESS; GATE RESISTANCE; GATE-LENGTH; HIGH-SPEED OPERATION; PERFORMANCE; ROOM-TEMPERATURE OPERATION; SELF ALIGNED SILICIDE PROCESS; SUBTHRESHOLD CHARACTERISTICS; SWITCHING DELAY;

CMOS INTEGRATED CIRCUITS;

SALICIDE PROCESS; SHEET RESISTANCE; SUBTHRESHOLD CHARACTERISTICS; SWITCHING DELAY;

EID: 0027889412     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. M.Iwas et al.IEEE Elec.Dev. Lett., vol.14, p.51 (1993).
2. G. G. Shahidi et al., VLSI Tech. Dig., p.93 (1993).
3. A. C. Berti et al., Proc. IEEE VMIC Conf., p.267 (1992).