Gate length scalability of n-MOSFET's down to 30 nm: Comparison between LDD and non-LDD structures

IEEE Transactions on Electron Devices

Volumn 47, Issue 4, 2000, Pages 835-840

  Murakami, Eiichi ^a   Yoshimura, Toshiyuki ^b   Goto, Yasushi ^a   Kimura, ShiN'ichiro ^b  

^a HITACHI LTD   (Japan)

^b Arthur D Little (Japan) Inc   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

DRAIN INDUCED BARRIER LOWERING (DIBL) METHODS; LIGHTLY DOPED DRAINS (LDD); SHORT-CHANNEL EFFECTS;

MOSFET DEVICES;

EID: 0033887043     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.831001     Document Type: Article

References (19)

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