Short channel MOSFET model using a universal channel depletion width parameter

IEEE Transactions on Electron Devices

Volumn 47, Issue 6, 2000, Pages 1202-1208

  Suzuki, Kunihiro ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY CONDITIONS; COMPUTER SIMULATION; DOPING (ADDITIVES); GATES (TRANSISTOR); MOSFET DEVICES; NUMERICAL ANALYSIS; PROBABILITY DISTRIBUTIONS; SEMICONDUCTOR DEVICE STRUCTURES; THRESHOLD VOLTAGE; TWO DIMENSIONAL;

CHANNEL DEPLETION WIDTH PARAMETER; JUNCTION DEPTH; POISSON EQUATION; POTENTIAL DISTRIBUTION; SCALING THEORY; SHORT CHANNEL EFFECTS; SOFTWARE PACKAGE FLAPS;

SEMICONDUCTOR DEVICE MODELS;

EID: 0033739984     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.842962     Document Type: Article

References (18)

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