Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET's Derived from Two-Dimensional Analysis

IEEE Transactions on Electron Devices

Volumn 26, Issue 4, 1979, Pages 453-461

  Toyabe, Toru ^a   Asai, Shojiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS - LARGE SCALE INTEGRATION;

SEMICONDUCTOR DEVICES, MIS;

EID: 0018454952     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1979.19448     Document Type: Article

References (8)

1. R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous, and A. LeBlanc, “Design of ion-implanted MOSFET's with very small physical dimensions IEEE J. Solid-State Circuits, vol. SC-9, pp. 256–268 Oct. 1974.
2. T. Toyabe, K. Yamaguchi, S. Asai, and M. S. Mock, “A numerical model of avalanche breakdown in MOSFET's IEEE Trans. Electron Devices, vol. ED-25, pp. 825–832, July 1978.
3. H. S. Lee, “An analysis of the threshold voltage for short-channel IGFET's Solid-State Electton., vol. 16, pp. 1407–1417,1973.
4. L. D. Yau, “A simple theory to predict the threshold voltage of short-channel IGFET's Solid-State Electron., vol. 17, pp. 1059–1063,1974.
5. M. S. Mock, “A two-dimensional mathematical model of the insulated-gate field-effect transistor Solid-State Electron., vol. 16, pp. 601–609, 1973.
6. H. Masuda, M. Nakai, R. Hori and M. Kubo “Device design of short channel MOS-FET‘s based on two dimensional numerical analysis program Trans. IECE Japan, vol. 60-C, pp. 205–212, 1977.
7. H. K. Gummel, “A self-consistent iterative scheme for one-dimensional steady state transistor calculations IEEE Trans. Electron Devices, vol. ED-11, pp. 455–465, 1964.
8. W. L. Brown, “n-type surface conductivity on p-type germanium Phys. Rev., vol. 91, pp. 518–527, Aug. 1953.