Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

Superlattices and Microstructures

Volumn 27, Issue 2, 2000, Pages 191-206

  Choi, Chang Hoon ^a   Yu, Zhiping ^a   Dutton, Robert W ^a  

^a Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CHARGE CARRIERS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; ELECTRON TUNNELING; GATES (TRANSISTOR); OPTIMIZATION; QUANTUM THEORY; SEMICONDUCTOR DEVICE MODELS;

CIRCUIT COMPACT MODELS;

MOS DEVICES;

EID: 0033735081     PISSN: 07496036     EISSN: None     Source Type: Journal    
DOI: 10.1006/spmi.1999.0799     Document Type: Article

References (15)

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