-
1
-
-
0020716756
-
-
31, pp. 260-265, May 1984.
-
J.W. Adams and A.N. Willson, "Some efficient digital prefilter structures," IEEE Trans. Circuits Syst., vol. 31, pp. 260-265, May 1984.
-
And A.N. Willson, Some Efficient Digital Prefilter Structures, IEEE Trans. Circuits Syst., Vol.
-
-
Adams, J.W.1
-
2
-
-
0028727716
-
-
2, pp. 426-36, Dec. 1994.
-
M. Alidina, J. Monterio, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-based sequential logic optimization for low-power," IEEE Trans. VLSI Syst., vol. 2, pp. 426-36, Dec. 1994.
-
J. Monterio, S. Devadas, A. Ghosh, and M. Papaefthymiou, Precomputation-based Sequential Logic Optimization for Low-power, IEEE Trans. VLSI Syst., Vol.
-
-
Alidina, M.1
-
3
-
-
0029231165
-
-
14, pp. 12-31, Jan. 1995.
-
A.P. Chandrakasan, M. Potkonjak, R. Mehra, J. Rabaey, and R.W. Broderson, "Optimizing power using transformations," IEEE Trans. Computer-Aided Design, vol. 14, pp. 12-31, Jan. 1995.
-
M. Potkonjak, R. Mehra, J. Rabaey, and R.W. Broderson, Optimizing Power Using Transformations, IEEE Trans. Computer-Aided Design, Vol.
-
-
Chandrakasan, A.P.1
-
4
-
-
0028728397
-
-
2, pp. 398-07, Dec. 1994.
-
W.C. Athas, L.J. Svensson, J.G. Koller, N. Tzartzanis, and E. Y.C. Chou, "Low-power digital systems based on adiabatic switching principles," IEEE J. Solid-State Circuits, vol. 2, pp. 398-07, Dec. 1994.
-
L.J. Svensson, J.G. Koller, N. Tzartzanis, and E. Y.C. Chou, Low-power Digital Systems Based on Adiabatic Switching Principles, IEEE J. Solid-State Circuits, Vol.
-
-
Athas, W.C.1
-
5
-
-
0029293575
-
-
83, pp. 498-523, Apr. 1995.
-
A. Chandrakasan and R.W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, vol. 83, pp. 498-523, Apr. 1995.
-
And R.W. Brodersen, Minimizing Power Consumption in Digital CMOS Circuits, Proc. IEEE, Vol.
-
-
Chandrakasan, A.1
-
6
-
-
0027969352
-
-
7th Int. Conf. VLSI Design, Calcutta, India, Jan. 1994, pp. 265-270.
-
A. Chatterjee and R.K. Roy, "Synthesis of low power linear DSP circuits using activity metrics," in Proc. 7th Int. Conf. VLSI Design, Calcutta, India, Jan. 1994, pp. 265-270.
-
And R.K. Roy, Synthesis of Low Power Linear DSP Circuits Using Activity Metrics, in Proc.
-
-
Chatterjee, A.1
-
7
-
-
0031641204
-
-
1998, pp. V-354-V-358.
-
J.-G. Chung, Y.-B. Kirn, H.-J. Jeong, and K.K. Parhi, "Efficient parallel FIR filter implementations using frequency spectrum characteristics," in Proc. IEEE Int. Symp. Circuits Syst., Monterey, CA, May-June 1998, pp. V-354-V-358.
-
Y.-B. Kirn, H.-J. Jeong, and K.K. Parhi, Efficient Parallel FIR Filter Implementations Using Frequency Spectrum Characteristics, in Proc. IEEE Int. Symp. Circuits Syst., Monterey, CA, May-June
-
-
Chung, J.-G.1
-
8
-
-
0029292445
-
-
83, pp. 595-606, Apr. 1995.
-
B. Davari, R.H. Dennard, and G.G. Shahidi, "CMOS scaling for highperformance and low-power-The next ten years," Proc. IEEE, vol. 83, pp. 595-606, Apr. 1995.
-
R.H. Dennard, and G.G. Shahidi, CMOS Scaling for Highperformance and Low-power-The next Ten Years, Proc. IEEE, Vol.
-
-
Davari, B.1
-
9
-
-
0029374075
-
-
42, pp. 569-577, Sept. 1995.
-
A.G. Dempster and M.D. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol. 42, pp. 569-577, Sept. 1995.
-
And M.D. Macleod, Use of Minimum-adder Multiplier Blocks in FIR Digital Filters, IEEE Trans. Circuits Syst. II, Vol.
-
-
Dempster, A.G.1
-
10
-
-
0030687370
-
-
1997, pp. 161-166.
-
M. Goel and N.R. Shanbhag, "Dynamic algorithm transformations (DAT) for low-power adaptive signal processing," in Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug. 1997, pp. 161-166.
-
And N.R. Shanbhag, Dynamic Algorithm Transformations (DAT) for Low-power Adaptive Signal Processing, in Int. Symp. Low Power Electronics and Design, Monterey, CA, Aug.
-
-
Goel, M.1
-
11
-
-
0022766771
-
-
505-513, Aug. 1986.
-
M. Hatamian and G.L. Cash, "Parallel pipelined multiplier," IEEE J. Solid-State Circuits, vol. SC-21, pp. 505-513, Aug. 1986.
-
And G.L. Cash, Parallel Pipelined Multiplier, IEEE J. Solid-State Circuits, Vol. SC-21, Pp.
-
-
Hatamian, M.1
-
12
-
-
0028736474
-
-
1994, pp. 8-11.
-
M. Horowitz, T. Indermaur, and R. Gonzalez, "Low-power digital design," in Proc. Symp. Low Power Electronics, San Diego, CA, Oct. 1994, pp. 8-11.
-
T. Indermaur, and R. Gonzalez, Low-power Digital Design, in Proc. Symp. Low Power Electronics, San Diego, CA, Oct.
-
-
Horowitz, M.1
-
13
-
-
0021624005
-
-
3, no. 3, pp. 267-294, 1984.
-
H.H. Loomis and B. Sinha, "High speed recursive digital filter realization," Circuit System and Signal Processing, vol. 3, no. 3, pp. 267-294, 1984.
-
And B. Sinha, High Speed Recursive Digital Filter Realization, Circuit System and Signal Processing, Vol.
-
-
Loomis, H.H.1
-
14
-
-
0030107942
-
-
31, pp. 395-00, Mar. 1996.
-
J.T. Ludwig, S.H. Nawab, and A.P. Chandrakasan, "Low-power digital filtering using approximate processing," J. Solid-State Circuits, vol. 31, pp. 395-00, Mar. 1996.
-
S.H. Nawab, and A.P. Chandrakasan, Low-power Digital Filtering Using Approximate Processing, J. Solid-State Circuits, Vol.
-
-
Ludwig, J.T.1
-
15
-
-
0031655507
-
-
1998, pp. 12-17.
-
M. Mehendale, S.D. Sherlekar, and G. Venkatesh, "Algorithmic and architectural transformations for low-power realization of FIR filters," in Proc. llth Int. Conf. VLSI Design, Chennai, India, Jan. 1998, pp. 12-17.
-
S.D. Sherlekar, and G. Venkatesh, Algorithmic and Architectural Transformations for Low-power Realization of FIR Filters, in Proc. Llth Int. Conf. VLSI Design, Chennai, India, Jan.
-
-
Mehendale, M.1
-
16
-
-
0031655083
-
-
1998, pp. 110-115.
-
M. Mehendale, S.B. Roy, S.D. Sherlekar, and G. Venkatesh, "Coefficient transformations for area-efficient implementation of multiplier-less FIR filters," in Proc. llth Int. Conf. VLSI Design, Chennai, India, Jan. 1998, pp. 110-115.
-
S.B. Roy, S.D. Sherlekar, and G. Venkatesh, Coefficient Transformations for Area-efficient Implementation of Multiplier-less FIR Filters, in Proc. Llth Int. Conf. VLSI Design, Chennai, India, Jan.
-
-
Mehendale, M.1
-
17
-
-
0026172340
-
-
39, pp. 1322-1332, June 1991.
-
Z.-J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Processing, vol. 39, pp. 1322-1332, June 1991.
-
And P. Duhamel, Short-length FIR Filters and Their Use in Fast Nonrecursive Filtering, IEEE Trans. Signal Processing, Vol.
-
-
Mou, Z.-J.1
-
18
-
-
0027575799
-
-
28, pp. 414-119, Apr. 1993.
-
Y. Nakagome, K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, "Sub1-V swing internal bus architecture for future low-power ULSI's," J. Solid-State Circuits, vol. 28, pp. 414-119, Apr. 1993.
-
K. Itoh, M. Isoda, K. Takeuchi, and M. Aoki, Sub1-V Swing Internal Bus Architecture for Future Low-power ULSI's, J. Solid-State Circuits, Vol.
-
-
Nakagome, Y.1
-
19
-
-
0024883413
-
-
77, pp. 1879-1895, Dec. 1989.
-
K.K. Parhi, "Algorithm transformation techniques for concurrent processors," Proc. IEEE, vol. 77, pp. 1879-1895, Dec. 1989.
-
Algorithm Transformation Techniques for Concurrent Processors, Proc. IEEE, Vol.
-
-
Parhi, K.K.1
-
20
-
-
0024700229
-
-
37, pp. 1099-1134, July 1989.
-
K.K. Parhi and D.G. Messerschmitt, "Pipeline interleaving and parallelism in recursive digital filters-Parts I, II," IEEE Trans. Acoust., Speech, Signal Processing, vol. 37, pp. 1099-1134, July 1989.
-
And D.G. Messerschmitt, Pipeline Interleaving and Parallelism in Recursive Digital Filters-Parts I, II, IEEE Trans. Acoust., Speech, Signal Processing, Vol.
-
-
Parhi, K.K.1
-
21
-
-
0029179528
-
-
1995, pp. 231-234.
-
D.N. Pearson and K.K. Parhi, "Low-power FIR digital filter architectures," IEEE Int. Symp. Circuits Syst., Seattle, WA, Apr.-May 1995, pp. 231-234.
-
And K.K. Parhi, Low-power FIR Digital Filter Architectures, IEEE Int. Symp. Circuits Syst., Seattle, WA, Apr.-May
-
-
Pearson, D.N.1
-
22
-
-
5544256331
-
-
1C design: Principles and applications, IEEE/ACM Trans. Design Automation of Electronic Systems, vol. 1, pp. 3-56, Jan. 1996.
-
M. Pedram, "Power minimization in 1C design: Principles and applications," IEEE/ACM Trans. Design Automation of Electronic Systems, vol. 1, pp. 3-56, Jan. 1996.
-
Power Minimization in
-
-
Pedram, M.1
-
23
-
-
0031636263
-
-
1998, pp. 250-255.
-
S. Ramprasad, N.R. Shanbhag, and I.N. Hajj, "Decorrelating (DECOR) transformations for low-power adaptive filters," in Int. Symp. Low-Power Electronics and Design, Monterey, CA, Aug. 1998, pp. 250-255.
-
N.R. Shanbhag, and I.N. Hajj, Decorrelating (DECOR) Transformations for Low-power Adaptive Filters, in Int. Symp. Low-Power Electronics and Design, Monterey, CA, Aug.
-
-
Ramprasad, S.1
-
24
-
-
0031168367
-
-
44, pp. 488-197, June 1997.
-
N. Sankarayya, K. Roy, and D. Bhattacharya, "Algorithms for low power and high speed FIR filter realization using differential coefficients," IEEE Trans. Circuits Syst. II, vol. 44, pp. 488-197, June 1997.
-
K. Roy, and D. Bhattacharya, Algorithms for Low Power and High Speed FIR Filter Realization Using Differential Coefficients, IEEE Trans. Circuits Syst. II, Vol.
-
-
Sankarayya, N.1
-
25
-
-
0031359374
-
-
1997, pp. 120-125.
-
N. Sankarayya, K. Roy, and D. Bhattacharya, "Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1997, pp. 120-125.
-
K. Roy, and D. Bhattacharya, Optimizing Computations in A Transposed Direct Form Realization of Floating-point LTI-FIR Systems, in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, San Jose, CA, Nov.
-
-
Sankarayya, N.1
-
26
-
-
0031146348
-
-
51.84 Mb/s ATM-LAN, IEEE Trans. Signal Processing, vol. 45, pp. 1276-1290, May 1997.
-
N.R. Shanbhag and M. Goel, "Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN," IEEE Trans. Signal Processing, vol. 45, pp. 1276-1290, May 1997.
-
And M. Goel, Low-power Adaptive Filter Architectures and Their Application to
-
-
Shanbhag, N.R.1
-
27
-
-
0027003872
-
-
1992, pp. 402-07.
-
A. Shen, A. Ghosh, S. Devadas, and K. Keutzer, "On average power dissipation and random pattern testability of CMOS combinational logic networks," in IEEE/ACM Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 1992, pp. 402-07.
-
A. Ghosh, S. Devadas, and K. Keutzer, on Average Power Dissipation and Random Pattern Testability of CMOS Combinational Logic Networks, in IEEE/ACM Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov.
-
-
Shen, A.1
|