Use of Minimum-Adder Multiplier Blocks in FIR Digital Filters

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 42, Issue 9, 1995, Pages 569-577

  Dempster, Andrew G ^a   Macleod, Malcolm D ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CALCULATIONS; COMPUTATIONAL COMPLEXITY; GRAPH THEORY; MULTIPLYING CIRCUITS; OPTIMIZATION; VLSI CIRCUITS;

CANONIC SIGNED DIGIT; MULTIPLIER BLOCKS;

DIGITAL FILTERS;

EID: 0029374075     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.466647     Document Type: Article

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