On average power dissipation and random pattern testability of CMOS combinatorial logic networks

IEEE/ACM International Conference on Computer-Aided Design

Volumn , Issue , 1992, Pages 402-407

  Shen, Amelia ^a   Ghosh, Abhijit ^a   Devadas, Srinivas ^a   Keutzer, Kurt ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC POWER MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MATHEMATICAL MODELS;

AVERAGE POWER DISSIPATION; RANDOM PATTERN TESTABILITY;

COMBINATORIAL CIRCUITS;

EID: 0027003872     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)