Algorithmic and architectural transformations for low power realization of FIR filters

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 12-17

  Mehendale, Mahesh ^a   Sherlekar, S D ^a   Venkatesh, G ^a  

^a TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; MACROS; MULTIPLYING CIRCUITS;

POWER REDUCTION;

DIGITAL FILTERS;

EID: 0031655507     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)