Minimizing Power Consumption in Digital CMOS Circuits

Proceedings of the IEEE

Volumn 83, Issue 4, 1995, Pages 498-523

  Chandrakasan, Anantha P ^a   Chandrakasan, Brodersen ^b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CORRELATION THEORY; DIGITAL INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; OPTIMIZATION; SYNCHRONIZATION;

ARCHITECTURE BASED VOLTAGE SCALING STRATEGY; BUFFERING; GLITCHING; LOGIC SPEED; PACKETIZATION; POWER CONSUMPTION REDUCTION; RESYNCHRONIZATION; SIGNAL CORRELATIONS; SUPPLY VOLTAGE; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0029293575     PISSN: 00189219     EISSN: 15582256     Source Type: Journal    
DOI: 10.1109/5.371964     Document Type: Article

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