Algorithms for low power and high speed FIR filter realization using differential coefficients

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 6, 1997, Pages 488-497

  Sankarayya, N ^a   Roy, Kaushik ^a   Bhattacharya, Debashis ^b  

^a Purdue University   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONVOLUTIONAL CODES; ENERGY DISSIPATION; STORAGE ALLOCATION (COMPUTER);

DIFFERENTIAL COEFFICIENTS;

DIGITAL FILTERS;

EID: 0031168367     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.592582     Document Type: Article

References (10)

1. A. Chatterjee and R. K. Roy, "Synthesis of low power linear DSP circuits using activity metrics," in 7th Int. Conf. VLSI Design, Jan. 1994, pp. 265-270.
2. A. G. Dempster and M. D. Macleod, "Use of minimum-adder multiplier blocks in FIR digital filters," IEEE Trans. Circuits Syst. II, vol. 42, pp. 569-577, Sept. 1995.
3. A. P. Chandrakashan and R. Brodersen, Low Power Digital CMOS Design. Boston, MA: Kluwer Academic, 1996.
4. A. V. Oppenheim and R. W. Schafer, Discrete-Time Signal Processing. Englewood Cliffs, NJ: Prentice Hall, 1989.
5. B. P. Brandt and B. A. Wooley, "A low-power, area-efficient digital filter for decimation and interpolation," IEEE J. Solid-State Circuits, vol. 29, pp. 679-687, June 1994.
6. K. Roy and S. Prasad, "Circuit activity based logic synthesis for low power reliable operations," IEEE Trans. VLSI Syst., vol. 1, pp. 503-513, Dec. 1993.
7. M. Mehendale, S. D. Sherlekar, and G. Venkatesh, "Coefficient optimization for low power realization of FIR filters," in IEEE Workshop on VLSI Signal Processing, Japan, 1995, pp. 352-361.
8. N. Sankarayya, K. Roy, and D. Bhattacharya, "Algorithms for low power FIR filter realization using differential coefficients," in 10th Int. Conf. VLSI Design, Jan. 1997, pp. 174-178.
9. R. Hartley, "Optimization of CSD multipliers for filter design," in IEEE Int. Symp. Circuits Syst., vol. 4, 1991, pp. 1992-1995.
10. T. Burd, "Low-power CMOS library design methodology," M.S. degree thesis, Univ. California, Berkeley, 1994.