Low-Power Digital Systems Based on Adiabatic-Switching Principles

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 4, 1994, Pages 398-407

  Athas, William C ^a   Svensson, J ^a   Koller, Jeffrey G ^a   Tzartzanis, Nestoras ^a   Chou, Ying Chin ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Adiabatic amplification; adiabatic charging; adiabatic switching; low power CMOS; reversible computation; switching energy reduction with preserved signal energies

Indexed keywords

AMPLIFICATION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ENERGY DISSIPATION; INTEGRATED CIRCUIT LAYOUT; SEQUENTIAL CIRCUITS; SWITCHING CIRCUITS; SWITCHING THEORY;

ADIABATIC AMPLIFICATION; ADIABATIC CHARGING; ADIABATIC SWITCHING; LOW POWER INTEGRATED CIRCUITS; REVERSIBLE COMPUTATION; SIGNAL ENERGY; SWITCHING ENERGY;

VLSI CIRCUITS;

EID: 0028728397     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.335009     Document Type: Article

References (16)

1. C. L. Seitz, A. H. Frey, S. Mattisson, S. D. Rabin, D. A. Speck, and J. L. A. van de Snepscheut, “Hot-clock NMOS,” in Proc. 1985 Chapel Hill Conf. VLSI, 1985, 1–17.
2. W. C. Athas, J. G. Koller, and L. “J.” Svensson, “An energy-efficient CMOS line driver using adiabatic switching,” Proc. Fourth Great Lakes Symp. VLSI Design, pp. 196–199, Mar. 1994.
3. A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circ., vol. 27, no. 4, pp. 473–484, April 1992.
4. C. A. Mead and L. Conway, Introduction to VLSI systems. Reading, MA: Addison-Wesley, 1980.
5. J. S. Hall, “An electroid switching model for reversible computer architectures,” in Proc. ICCI’92, 4th Int. Conf. on Computing and Information, 1992.
6. J. G. Koller and W. C. Athas, “Adiabatic switching, low energy computing, and the physics of storing and erasing information,” in Proc. Workshop on Physics and Computation, PhysCmp ’92, Oct. 1992; IEEE Press, 1993.
7. C. H. Bennett, “Logical reversibility of computation,” IBM J. Res. Dev., vol. 17, pp. 525–532, 1973.
8. R. Landauer, “Irreversibility and heat generation in the computing process,” IBM J. Res. Dev., vol. 5, pp. 183–191, 1961.
9. S. G. Younis and T. F. Rnight, “Practical implementation of charge recovery asymptotically zero power CMOS,” in Proc. 1993 Symp. on Integrated Syst., MIT Press, 1993, pp. 234–250.
10. C. H. Bennett and R. Landauer, “The fundamental physical limits of computation,” Scientific American, 48–56, July 1985.
11. R. Merkle, “Reversible electronic logic using switches,” Nanotechnology, vol. 4, pp. 21–40, 1993.
12. C. H. Bennett, “Time/space trade-offs for reversible computation,” SIAM J. Computing, vol. 18, 766–776, 1989.
13. E. M. Cherry and D. E. Hooper, Amplifying Devices and Low-Pass Amplifier Design. New York: Wiley, 1968.
14. A. Rramer, J. S. Denker, S. C. Avery, A. G. Dickinson, and T. R. Wik, “Adiabatic computing with the 2N-2N2D logic family,” in 1994 Symp. VLSI Circ.: Digest of Tech. Papers, IEEE Press, June 1994.
15. P. J. Duncan, S. Swamy, and R. Jain, “Low-power DSP circuit design using bit-level pipelined maximally parallel architectures,” in Proc. 1993 Symp. on Integrated Syst., MIT Press, 1993, pp. 266–275.
16. D. Maksimovic, “A MOS gate drive with resonant transitions,” in Proc. IEEE Power Electron. Specialists Conf, IEEE Press, 1991, pp. 527–532.