A 70-MHz 8-bit X 8-bit Parallel Pipelined Multiplier in 2.5-µm CMOS

IEEE Journal of Solid-State Circuits

Volumn 21, Issue 4, 1986, Pages 505-513

  Hatamian, Mehdi ^a   Cash, Glenn L ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS - MULTIPLYING CIRCUITS; ELECTRIC NETWORKS - COMPUTER SIMULATION; ELECTRONIC CIRCUITS, TIMING; INTEGRATED CIRCUITS, VLSI; SIGNAL PROCESSING - DIGITAL TECHNIQUES;

CLOCK DISTRIBUTION NETWORK; CMOS TECHNOLOGY; PIPELINED MULTIPLIERS; SOLID STATE CIRCUITS;

SEMICONDUCTOR DEVICES, MOS;

EID: 0022766771     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1986.1052564     Document Type: Article

References (15)

1. M. Hatamian and G. L. Cash, “High speed signal processing, pipelining, and VLSI,” in Proc. IEEE Int: Conf. Acoustics, Speech, and Signal 1986, 1173–1176.
2. J. V. McCanny D. Phil, and J. G. McWhirter, “Completely iterative, pipelined multiplier array suitable for VLSI,” Proc. Inst. Elec. Eng. vol. 129, Pt.G, no. 2, 40–46, Apr. 1982.
3. P. R. Cappello and K. Steiglitz, “A VLSI layout for a pipelines Dadda multiplier,” ACM Trans. Computer Syst., vol. 1, no. 2, pp. 157–174, May 1983.
4. C. E. Hauck, C. S. Bamji, and J. Allen, “The systematic exploration of pipelined array multiplier, performance,” in Proc. Int. Conf. Acoustics, Speech, and Signal Processing, Mar. 1985, pp. 1461–1463.
5. C. S. Bamji, C. E. Hauck, and J. Allen, “A design by example regular structure generator,” in Proc. IEEE 22nd Design Automation Conf., 1985, pp. 16–22.
6. P. R. Cappello and K. Steiglitz, “Completely pipelined architectures for digital signal processing,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP-31, no. 4, pp. 1016–1023, Aug. 1983.
7. D. A. Henlin, M. T. Fertsch, M. Mazin, and E. T. Lewis, “A 16 bit×16 16 bit pipelined multiplier macrocell,” IEEE J. Solid-State Circuits, vol. SC-20, no. 2, pp. 542–547, Apr. 1985.
8. F. P. J. M. Welten, J. Lohstroh, and A. J. Linssen, “A 25/50 MHz dual-model parallel multiplier/accumulator,” in Proc. IEEE Int. Solid-State Circuit Conf. Feb. 1984, pp. 86–87.
9. B. Ackland and N. Weste, “Functional verification in an interactive symbolic IC design environment,” in Proc. 2nd Caltech Conf. VLSI, Jan. 1981, pp. 285–298.
10. N. Weste, “MULGA-An interactive symbolic layout system for the design of integrated circuits,” Bell Syst. Tech. J., vol. 60, no. 6, pp. 823–858, July–Aug. 1981.
11. N. Weste, “Virtual grid symbolic layout,” in Proc. 18th Design Automation Conf., June 1981, pp. 225–233.
12. B. Ackland and N. Weste, “An automatic assembly tool for virtual grid symbolic layout,” in VLSI'83, F. Anceau and E. J. Aas, Eds. New York: Elsevier, pp. 457–466.
13. F. S. Lee et al., “A high speed GaAs 8×8 bit parallel multiplier,” IEEE J. Solid-State Circuits, vol. SC-17, no. 4, pp. 638–645, Aug. 1982.
14. G. Rabbat, Ed., Hardware and Software Concepts in VLSI. New York: Van Nostrand Reinhold, 1983, 282–292.
15. C. R. Baugh and B. A. Wooley, “A two's complement parallel array multiplication algorithm,” IEEE Trans. Computers vol. C-22, no. 12, pp. 1045–1047, Dec. 1973.