Multilevel logic synthesis for arithmetic functions

Proceedings - Design Automation Conference

Volumn , Issue , 1996, Pages 242-247

  Tsai, Chien Chung ^a   Marek Sadowska, Malgorzata ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; BOOLEAN FUNCTIONS; COMPUTER AIDED DESIGN; DIGITAL ARITHMETIC; LOGIC CIRCUITS; LOGIC GATES;

ALGEBRAIC FACTORIZATION; ARITHMETIC FUNCTIONS; MULTILEVEL LOGIC SYNTHESIS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0029717581     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/240518.240563     Document Type: Conference Paper

References (22)