Logic synthesis for testability

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1996, Pages 118-121

  Tsai, Ch Ch ^a   Marek Sadowska, M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; NETWORKS (CIRCUITS); PATTERN RECOGNITION; TESTING;

PATTERN GENERATION;

COMPUTER AIDED LOGIC DESIGN;

EID: 0029695715     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)