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Volumn , Issue , 1996, Pages 148-154

AND/EXOR-based synthesis of testable KFDD-circuits with small depth

Author keywords

[No Author keywords available]

Indexed keywords

EXOR GATES; KRONECKER FUNCTIONAL DECISION DIAGRAMS (KFDD);

EID: 0030381186     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (20)
  • 2
    • 0022769976 scopus 로고
    • Graph-based algorithms for Boolean function manipulation
    • R.E. Bryant. Graph-based algorithms for Boolean function manipulation. IEEE Trans. on Comp., 8:677-691, 1986.
    • (1986) IEEE Trans. on Comp , vol.8 , pp. 677-691
    • Bryant, R.E.1
  • 3
    • 0028594117 scopus 로고
    • Efficient representation and manipulation of switching functions based on ordered kronecker functional decision diagrams
    • R. Drechsler, A. Sarabi, M. Theobald, B. Becker, and M.A. Perkowski. Efficient representation and manipulation of switching functions based on Ordered Kronecker Functional Decision Diagrams. In Design Automation Conf., pages 415-419, 1994.
    • (1994) Design Automation Conf , pp. 415-419
    • Drechsler, R.1    Sarabi, A.2    Theobald, M.3    Becker, B.4    Perkowski, M.A.5
  • 5
    • 0026676489 scopus 로고
    • Gate-delayfault testability properties of multiplexor-based networks
    • P. Ashar, S. Devadas, and K. Keutzer. Gate-delayfault testability properties of multiplexor-based networks. In Int'l Test Conf., pages 887-896, 1991.
    • (1991) Int'l Test Conf , pp. 887-896
    • Ashar, P.1    Devadas, S.2    Keutzer, K.3
  • 7
    • 0027634507 scopus 로고
    • Path-delayfault testability properties of multiplexor-based networks
    • P. Ashar, S. Devadas, and K. Keutzer. Path-delayfault testability properties of multiplexor-based networks. Integration the VLSI Jour., 15(1):1-23, 1993.
    • (1993) Integration the VLSI Jour , vol.15 , Issue.1 , pp. 1-23
    • Ashar, P.1    Devadas, S.2    Keutzer, K.3
  • 9
    • 33749951565 scopus 로고
    • Synthesis for testability: Circuits derived from ordered kronecker functional decision diagrams
    • B. Becker and R. Drechsler. Synthesis for testability: Circuits derived from ordered kronecker functional decision diagrams. In European Design & Test Conf., page 592, 1995.
    • (1995) European Design & Test Conf , pp. 592
    • Becker, B.1    Drechsler, R.2
  • 11
    • 0009767309 scopus 로고
    • Synthesis of multi-level logic circuits from binary decision diagrams
    • N. Ishiura. Synthesis of multi-level logic circuits from binary decision diagrams. In SASIMI, pages 74-83, 1992.
    • (1992) SASIMI , pp. 74-83
    • Ishiura, N.1
  • 16
    • 0027841555 scopus 로고
    • Dynamic variable ordering for ordered binary decision diagrams
    • R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In Int'l Conf. on CAD, pages 42-47, 1993
    • (1993) Int'l Conf. on CAD , pp. 42-47
    • Rudell, R.1
  • 20
    • 0003047401 scopus 로고
    • Automated logic synthesis of random pattern testable circuits
    • N.A. Touba and E.J. McCluskey. Automated logic synthesis of random pattern testable circuits. In Int'l Test Conf., pages 174-183, 1994.
    • (1994) Int'l Test Conf , pp. 174-183
    • Touba, N.A.1    McCluskey, E.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.