-
1
-
-
0024684021
-
Drain-engineered hotelectron-resistant device structures: A review
-
1125, June 1989.
-
J. J. Sanchez, K. K. Hsueh, and T. A. DeMassa, Drain-engineered hotelectron-resistant device structures: A review, IEEE Trans. Electron Devices, vol. 36, p. 1125, June 1989.
-
IEEE Trans. Electron Devices, Vol. 36, P.
-
-
Sanchez, J.J.1
Hsueh, K.K.2
DeMassa, T.A.3
-
2
-
-
0025522137
-
Limitations of LDD types of structures in deep-submicrometer MOS technology
-
1990.
-
A. F. Tasch, H. Shin, T. J. Bordelon, and C. M. Maziar, Limitations of LDD types of structures in deep-submicrometer MOS technology, IEEE Electron Device Lett., vol. 11, p. 517, Nov. 1990.
-
IEEE Electron Device Lett., Vol. 11, P. 517, Nov.
-
-
Tasch, A.F.1
Shin, H.2
Bordelon, T.J.3
Maziar, C.M.4
-
3
-
-
0025578211
-
Drain structure optimization for highly reliable deep submicron nMOSFET's with 3.3 V high-performance operation
-
1990, p. 833.
-
F. Matsuoka, K. Kasai, H. Oyamatsu, M. Kinugawa, and K. Maeguchi, Drain structure optimization for highly reliable deep submicron nMOSFET's with 3.3 V high-performance operation, in IEDM Tech. Dig., 1990, p. 833.
-
In IEDM Tech. Dig.
-
-
Matsuoka, F.1
Kasai, K.2
Oyamatsu, H.3
Kinugawa, M.4
Maeguchi, K.5
-
4
-
-
84954143657
-
A sub-half-micron partially gate-to-drain overlapped MOSFET optimized for high performance and reliability
-
1991, p. 545.
-
I. C. Chen, R. A. Chapman, and C. W. Teng, A sub-half-micron partially gate-to-drain overlapped MOSFET optimized for high performance and reliability, in IEDM Tech. Dig., 1991, p. 545.
-
In IEDM Tech. Dig.
-
-
Chen, I.C.1
Chapman, R.A.2
Teng, C.W.3
-
5
-
-
0024125821
-
The influence of tilted source-drain implants on high-field effects in submicrometer MOSFET's
-
2119, Dec. 1988.
-
F. K. Baker and J. R. Pfiester, The influence of tilted source-drain implants on high-field effects in submicrometer MOSFET's, IEEE Trans. Electron Devices, vol. 35, p. 2119, Dec. 1988.
-
IEEE Trans. Electron Devices, Vol. 35, P.
-
-
Baker, F.K.1
Pfiester, J.R.2
-
6
-
-
0024870094
-
Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-halfmicron n-MOSFET design for reliability and performance
-
1989, p. 617.
-
T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, Asymmetrical halo source GOLD drain (HS-GOLD) deep sub-halfmicron n-MOSFET design for reliability and performance, in IEDM Tech. Dig., 1989, p. 617.
-
In IEDM Tech. Dig.
-
-
Buti, T.N.1
Ogura, S.2
Rovedo, N.3
Tobimatsu, K.4
Codella, C.F.5
-
7
-
-
0021489601
-
Source-and-drain series resistance of LDD MOSFET's
-
1984.
-
B. J. Sheu, C. Hu, P. K. Ko, and F.-C. Hsu, Source-and-drain series resistance of LDD MOSFET's, IEEE Electron Lett., Vol. EDL5, p. 365, Sept. 1984.
-
IEEE Electron Lett., Vol. EDL5, P. 365, Sept.
-
-
Sheu, B.J.1
Hu, C.2
Ko, P.K.3
Hsu, F.-C.4
-
9
-
-
0021119799
-
An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices
-
1984.
-
C. Duvvury, D. Baglee, M. Duane, A. Hyslop, M. Smayling, and M. Maekawa, An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices, Solid State Electron., vol. 27, p. 89, 1984.
-
Solid State Electron., Vol. 27, P. 89
-
-
Duvvury, C.1
Baglee, D.2
Duane, M.3
Hyslop, A.4
Smayling, M.5
Maekawa, M.6
-
10
-
-
0023570547
-
Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's
-
2469, Dec. 1987.
-
G. J. Hu, C. Chang, and Y.-T. Chia, Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's, IEEE Trans. Electron Devices, Vol. ED34, p. 2469, Dec. 1987.
-
IEEE Trans. Electron Devices, Vol. ED34, P.
-
-
Hu, G.J.1
Chang, C.2
Chia, Y.-T.3
-
11
-
-
0027656616
-
A new approach to determine the drainand-source series resistance of LDD MOSFET's
-
1709, Sept. 1993.
-
S. S.-S. Chung and J.-S. Lee, A new approach to determine the drainand-source series resistance of LDD MOSFET's, IEEE Trans. Electron Devices, vol. 40, p. 1709, Sept. 1993.
-
IEEE Trans. Electron Devices, Vol. 40, P.
-
-
Chung, S.S.-S.1
Lee, J.-S.2
-
12
-
-
0028517119
-
A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's
-
1811, Oct. 1994.
-
J.-C. Guo, S. S.-S. Chung, and C. C.-H. Hsu, A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's, IEEE Trans. Electron Devices, vol. 41, p. 1811, Oct. 1994.
-
IEEE Trans. Electron Devices, Vol. 41, P.
-
-
Guo, J.-C.1
Chung, S.S.-S.2
Hsu, C.C.-H.3
-
13
-
-
0030151214
-
An efficient method for determining threshold voltage, series resistance, and effective geometry of MOS transistors
-
1996.
-
P. R. Karlsson and K. O. Jeppson, An efficient method for determining threshold voltage, series resistance, and effective geometry of MOS transistors, IEEE Trans. Semiconduct. Manufact., vol. 9, p. 215, May 1996.
-
IEEE Trans. Semiconduct. Manufact., Vol. 9, P. 215, May
-
-
Karlsson, P.R.1
Jeppson, K.O.2
-
14
-
-
0024682748
-
Parameter extraction from I-V characteristics of single MOSFET's
-
1094, June 1989.
-
L. Selmi, E. Sangiorgi, and B. Ricco, Parameter extraction from I-V characteristics of single MOSFET's, IEEE Trans. Electron Devices, vol. 36, p. 1094, June 1989.
-
IEEE Trans. Electron Devices, Vol. 36, P.
-
-
Selmi, L.1
Sangiorgi, E.2
Ricco, B.3
-
15
-
-
49549126543
-
Electron scattering in silicon inversion layers by oxide and surface roughness
-
1976.
-
A. Hartstein, T. H. Ning, and A. B. Fowler, Electron scattering in silicon inversion layers by oxide and surface roughness, Surf. Sei., vol. 58, p. 178, 1976.
-
Surf. Sei., Vol. 58, P. 178
-
-
Hartstein, A.1
Ning, T.H.2
Fowler, A.B.3
-
16
-
-
0019048875
-
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surface
-
1497, Aug. 1980.
-
S. C. Sun and J. D. Plummer, Electron mobility in inversion and accumulation layers on thermally oxidized silicon surface, IEEE Trans. Electron Devices, Vol. ED27, p. 1497, Aug. 1980.
-
IEEE Trans. Electron Devices, Vol. ED27, P.
-
-
Sun, S.C.1
Plummer, J.D.2
-
17
-
-
0023596537
-
Universal mobility-field curves for electrons and holes in MOS inversion layers
-
1987, p. 81.
-
J. T. Watt and J. D. Plummer, Universal mobility-field curves for electrons and holes in MOS inversion layers, in Symp. VLSI Technol. Dig. Tech. Papers, 1987, p. 81.
-
In Symp. VLSI Technol. Dig. Tech. Papers
-
-
Watt, J.T.1
Plummer, J.D.2
-
18
-
-
0025439799
-
Extraction of MOSFET carrier mobility characteristics and calibration of a mobility model for numerical device simulation
-
1990.
-
S.-W. Lee, Extraction of MOSFET carrier mobility characteristics and calibration of a mobility model for numerical device simulation, Solid State Electron., vol. 33, p. 719, 1990.
-
Solid State Electron., Vol. 33, P. 719
-
-
Lee, S.-W.1
-
19
-
-
0027846942
-
Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction
-
1993, p. 515.
-
V. H. Chan and J. E. Chung, Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction, in IEDM Tech. Dig., 1993, p. 515.
-
In IEDM Tech. Dig.
-
-
Chan, V.H.1
Chung, J.E.2
-
20
-
-
84907819006
-
The voltage dependence of degradation in N-MOS transistors
-
1988.
-
B. S. Doyle, M. Bourcerie, J.-D. Marchetaux, and A. Boudou, The voltage dependence of degradation in N-MOS transistors, Solid-State Devices, p. 257, 1988.
-
Solid-State Devices, P. 257
-
-
Doyle, B.S.1
Bourcerie, M.2
Marchetaux, J.-D.3
Boudou, A.4
-
21
-
-
0028756531
-
Hot-carrier induced electron mobility and series resistance degradation in LDD NMOSFET's
-
1994.
-
Y. Pan, K. K. Ng, and C. C. Wei, Hot-carrier induced electron mobility and series resistance degradation in LDD NMOSFET's, IEEE Electron Device Lett., vol. 15, p. 499, Dec. 1994.
-
IEEE Electron Device Lett., Vol. 15, P. 499, Dec.
-
-
Pan, Y.1
Ng, K.K.2
Wei, C.C.3
-
23
-
-
0004161838
-
-
1995, p. 683.
-
W. H. Press, S. A. Teukolsky, W. T. Vettering, and B. P. Flannery, Numerical Recipes in C, 2nd ed. Cambridge, U.K.: Cambridge Univ. Press, 1995, p. 683.
-
Numerical Recipes in C, 2nd Ed. Cambridge, U.K.: Cambridge Univ. Press
-
-
Press, W.H.1
Teukolsky, S.A.2
Vettering, W.T.3
Flannery, B.P.4
-
24
-
-
0028392709
-
A capacitance-based method for experimental determination of metallurgical channel length of submicron MOSFET's
-
1994.
-
S.-W. Lee, A capacitance-based method for experimental determination of metallurgical channel length of submicron MOSFET's, IEEE Trans. Electron Devices, vol. 41, p. 403, Mar. 1994.
-
IEEE Trans. Electron Devices, Vol. 41, P. 403, Mar.
-
-
Lee, S.-W.1
-
25
-
-
0026938421
-
Deep-submicrometer largeangle-tilt implanted drain (LATID) technology
-
2312, Oct. 1992.
-
T. Hori, J. Hirase, Y. Odake, and T. Yasui, Deep-submicrometer largeangle-tilt implanted drain (LATID) technology, IEEE Trans. Electron Devices, vol. 39, p. 2312, Oct. 1992.
-
IEEE Trans. Electron Devices, Vol. 39, P.
-
-
Hori, T.1
Hirase, J.2
Odake, Y.3
Yasui, T.4
-
26
-
-
0022688857
-
Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET's
-
1986.
-
M. S. Liang, J. Y. Choi, P. K. Ko, and C. Hu, Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET's, IEEE Trans. Electron Device, Vol. ED33, p. 409, Mar. 1986.
-
IEEE Trans. Electron Device, Vol. ED33, P. 409, Mar.
-
-
Liang, M.S.1
Choi, J.Y.2
Ko, P.K.3
Hu, C.4
-
27
-
-
0026187962
-
-
1991.
-
Y. T. Yeow, C. H. Ling, and L. K. Ah, Observation of MOSFET degradation due to electrical stressing through gate-to-source and gateto-drain capacitance measurement,IEEEElectron Device Lett., vol. 12, p. 366, July 1991.
-
Observation of MOSFET degradation due to electrical stressing through gate-to-source and gateto-drain capacitance measurement,IEEEElectron Device Lett., vol. 12, p. 366, July
-
-
Yeow, Y.T.1
Ling, C.H.2
Ah, L.K.3
|