Approaches to extra low voltage dram operation by soi-dram

IEEE Transactions on Electron Devices

Volumn 45, Issue 5, 1998, Pages 1000-1009

  Eimori, Takahisa ^a   Oashi, Toshiyuki ^b   Morishita, Fukashi ^a   Iwamatsu, Toshiaki ^a   Yamaguchi, Yasuo ^a   Okuda, Fumihiro ^a   Shimomura, KeN'Ichi ^a   Shimano, Hiroki ^b   Sakashita, Narumi ^a   Arimoto, Kazutami ^a   Inoue, Yasuo ^b   Komori, Shinji ^a   Inuishi, Masahide ^a   Nishimura, Tadashi ^a   Miyoshi, Hirokazu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b LTEC Corp   (Japan)

Author keywords

DRAM; High speed circuits devices; Silicon oninsulator

Indexed keywords

CAPACITANCE; CAPACITORS; DIELECTRIC FILMS; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY;

BODY BIAS CONTROL TECHNIQUES; DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0032075636     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.669509     Document Type: Article

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