Low-voltage operation of a high-resistivity load SOI SRAM cell by reduced back-gate-bias effect

IEICE Transactions on Electronics

Volumn E78-C, Issue 7, 1995, Pages 812-817

  Yamaguchi, Yasuo ^a   Takahashi, Jun ^a   Yamaguchi, Takehisa ^a   Wada, Tomohisa ^a   Iwamatsu, Toshiaki ^a   Joachim, Hans Oliver ^a   Inoue, Yasuo ^a   Nishimura, Tadashi ^a   Tsubouchi, Natsuro ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FABRICATION; MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THIN FILMS;

BACK-GATE-BIAS; LOW VOLTAGE OPERATION; MULTIMEDIA SYSTEMS; STATIC RANDOM ACCESS MEMORY; VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 0029341020     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)