16Mb DRAM/SOI Technologies for Sub-1V Operation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 609-612

  Oashi, T ^a   Eimori, T ^a   Morishita, F ^a   Iwamatsu, T ^a   Yamaguchi, Y ^a   Okuda, F ^b   Shimomura, K ^a   Shimano, H ^a   Sakashita, N ^a   Arimoto, K ^a   Inoue, Y ^a   Komori, S ^a   Inuishi, M ^a   Nishimura, T ^a   Miyoshi, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

^b LTEC Corporation   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BODY FLOATING; BODY TIED; DUAL-GATE CMOS; FLOATING BODIES; FUNCTIONAL OPERATION; LOW SUPPLY VOLTAGES; LOW VOLTAGES; MOSFETS; PARASITICS; SOI TECHNOLOGY;

MOSFET DEVICES; CELLULAR ARRAYS;

CAPACITORS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DEGRADATION; GATES (TRANSISTOR); ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION; RANDOM ACCESS STORAGE; SILICON ON INSULATOR TECHNOLOGY;

DYNAMIC RANDOM ACCESS MEMORIES; ISOLATION TECHNOLOGY;

EID: 0030422230     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554057     Document Type: Conference Paper

References (3)

1. [l]T.Eimori, T.Oashi, H.Kimura, Y.Yamaguchi, T.Iwamatsu, T.Tsuruda, K.Suma, H.Hidaka,Y.Inoue,T.Nishimw S.Satohand H.Miyoshi,IEDMTech. Dig., p45,(1993)
2. H.S.Kim, S.B.Lee,D.U.Choi, J.H.Shim,K.C.Lee, K.P.Lee, K.N.Kimand J.W.Park; VLSI Symp. Tech. Dig., p.143, (1995)
3. F.Morishita,K. Suma, M.Hirose,T.Tsuruda, Y.Yamaguchi,T.Eimori,T.Oashi, K.Arimoto, Y.Inoue and T.Nishimura;VLSI Symp.Tech. Dig., p.141, (1995)