Circuit synthesis of clock distribution networks based on non-zero clock skew

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1994, Pages 175-178

  Neves, Jose Luis ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; MATHEMATICAL MODELS; TELECOMMUNICATION NETWORKS; TELECOMMUNICATION REPEATERS;

CLOCK DISTRIBUTION NETWORKS; INVERTER DELAY MODELS; NON ZERO CLOCK SKEW;

TIMING CIRCUITS;

EID: 0028564083     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)