-
2
-
-
0038670909
-
Elimination of process-dependent clock skew in CMOS VLSI
-
Oct.
-
M. Shoji, “Elimination of process-dependent clock skew in CMOS VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, no. 5, pp. 875–880, Oct. 1986.
-
(1986)
IEEE J. Solid-State Circuits
, vol.SC-21
, Issue.5
, pp. 875-880
-
-
Shoji, M.1
-
3
-
-
0019665885
-
Verification of timing constraints on large digital systems
-
T. M. McWilliams, “Verification of timing constraints on large digital systems,” J. Digital Syst., vol. 5, no. 4, pp. 401–427, 1981.
-
(1981)
J. Digital Syst.
, vol.5
, Issue.4
, pp. 401-427
-
-
McWilliams, T.M.1
-
4
-
-
84982646697
-
Circuit implementation of high-speed pipeline systems
-
L. W. Cotten, “Circuit implementation of high-speed pipeline systems,” in AFIPS Proc. 1965 Fall Joint Comput. Conf., vol. 27, pp. 489–504.
-
AFIPS Proc. 1965 Fall Joint Comput. Conf.
, vol.27
, pp. 489-504
-
-
Cotten, L.W.1
-
7
-
-
0024480668
-
Sizing an inverter with a precise delay: Generation of complementary signals with minimal skew and pulse width distortion in CMOS
-
Jan.
-
P. V. Argade, “Sizing an inverter with a precise delay: Generation of complementary signals with minimal skew and pulse width distortion in CMOS,” IEEE Trans. Comput.-Aided Design, vol. CAD-8, no. 1, pp. 33–40, Jan. 1989.
-
(1989)
IEEE Trans. Comput.-Aided Design
, vol.CAD-8
, Issue.1
, pp. 33-40
-
-
Argade, P.V.1
-
8
-
-
0003915801
-
SPICE2: A computer program to simulate semiconductor circuits
-
Memo ERL-M520, Univ. of California, Berkeley, May 9
-
L. W. Nagel, “SPICE2: A computer program to simulate semiconductor circuits,” Memo ERL-M520, Univ. of California, Berkeley, May 9, 1975.
-
(1975)
-
-
Nagel, L.W.1
-
10
-
-
0017982275
-
The PORT mathematical subroutine library
-
June
-
P. A. Fox and N. L. Schryer, “The PORT mathematical subroutine library,” ACM Trans. Math. Software, vol. 4, no. 2, pp. 104–126, June 1978.
-
(1978)
ACM Trans. Math. Software
, vol.4
, Issue.2
, pp. 104-126
-
-
Fox, P.A.1
Schryer, N.L.2
-
12
-
-
0020504458
-
Optimizing synchronous circuitry by retiming
-
R. Bryant, Ed.
-
C. E. Leiserson, F. M. Rose, and J. B. Saxe, “Optimizing synchronous circuitry by retiming,” in Proc. Third Caltech Conf. Very Large Scale Integration, R. Bryant, Ed., 1983, pp. 87–116.
-
(1983)
Proc. Third Caltech Conf. Very Large Scale Integration
, pp. 87-116
-
-
Leiserson, C.E.1
Rose, F.M.2
Saxe, J.B.3
-
14
-
-
0022231945
-
TILOS: A posynomial programming approach to transistor sizing
-
Santa Clara, CA, Nov.
-
J. P. Fishburn and A. E. Dunlop, “TILOS: A posynomial programming approach to transistor sizing,” in Proc. IEEE Int. Conf. Comput.-Aided Design (ICCAD-85), Santa Clara, CA, Nov. 1985, pp. 326–328.
-
(1985)
Proc. IEEE Int. Conf. Comput.-Aided Design (ICCAD-85)
, pp. 326-328
-
-
Fishburn, J.P.1
Dunlop, A.E.2
-
15
-
-
0000101622
-
Geometric programming: Methods, computations and applications
-
July
-
J. G. Ecker, “Geometric programming: Methods, computations and applications,” SIAM Rev., vol. 22, no. 3, pp. 338–362, July 1980.
-
(1980)
SIAM Rev.
, vol.22
, Issue.3
, pp. 338-362
-
-
Ecker, J.G.1
-
16
-
-
0020778211
-
Signal delay in RC tree networks
-
July
-
J. Rubinstein, P. Penfield, and M. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. Comput.-Aided Design, vol. CAD-2, no. 3, pp. 202–211, July 1983.
-
(1983)
IEEE Trans. Comput.-Aided Design
, vol.CAD-2
, Issue.3
, pp. 202-211
-
-
Rubinstein, J.1
Penfield, P.2
Horowitz, M.3
|