Optimization of critical paths in circuits with level-sensitive latches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 468-473

  Burks, Timothy M ^a   Sakallah, Karem A ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; FLIP FLOP CIRCUITS; GRAPHIC METHODS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS);

CIRCUIT COMPUTATION TIME; CONSTRAINT GRAPH; CRITICAL PATHS; CYCLE STEALING; LATE SIGNAL TIMING PROBLEMS; LEVEL SENSITIVE LATCHES;

LOGIC DESIGN;

EID: 0028699244     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (15)