Unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Volumn , Issue , 1993, Pages 220-223

  Chuang, Weitong ^a   Sapatnekar, Sachin S ^a   Hajj, Ibrahim N ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION;

CLOCK SKEW OPTIMIZATION; DELAY SPECIFICATION; GATE SIZING; STANDARD CELL PARADIGM; SYNCHRONOUS SEQUENTIAL CIRCUIT;

SEQUENTIAL CIRCUITS;

EID: 0027839526     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)