A 250-MHz skewed-clock pipelined data buffer

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 3, 1996, Pages 376-383

  Heshami, Mehrdad ^{a,b,c,d,e,f,g}   Wooley, Bruce A ^{a,b,d,h,i,j,k,l,m}  

^a IEEE

^b Stanford University   (United States)

^c SHARIF UNIVERSITY OF TECHNOLOGY   (Iran)

^d STANFORD UNIVERSITY   (United States)

^e Chrontel Inc   (United States)

^f HEWLETT PACKARD COMPANY   (United States)

^g Rockwell International   (United States)

^h UNIVERSITY OF CALIFORNIA   (United States)

ⁱ LUCENT TECHNOLOGIES   (United States)

^j Integrated Circuits Laboratory

^k IEEE Journal Of Solid State Circuits ^*

^l Prog Comm Symposium Low Pwr E

^m JTECH Panel Telecom Technology

more..

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; CODING ERRORS; COMPUTER ARCHITECTURE; DECODING; ENCODING (SYMBOLS); ERROR CORRECTION; FIBER OPTIC NETWORKS; INTEGRATED CIRCUIT MANUFACTURE; PIPELINE PROCESSING SYSTEMS; RANDOM ACCESS STORAGE;

BIT LINE BIASING; DEMULTIPLEXING; ON CHIP HAMMING ERROR CORRECTION CODING; PIPELINED DATA BUFFER; SKEWED CLOCK PIPELINING; STATIC RANDOM ACCESS MEMORY CELL; SYNCHRONOUS DUAL PORT MEMORY; SYNCHRONOUS OPTICAL NETWORKS;

BUFFER STORAGE;

EID: 0030107697     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.494199     Document Type: Article

References (11)

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