Clock System Design

IEEE Design and Test of Computers

Volumn 5, Issue 5, 1988, Pages 9-27

  Wagner, Kenneth D ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY -- FINITE AUTOMATA; ELECTRONIC CIRCUITS, FLIP FLOP; ELECTRONIC CIRCUITS, TIMING; LOGIC DESIGN; PULSE WIDTH MODULATION;

CLOCK DISTRIBUTION NETWORKS; COMPUTER CLOCK SYSTEM; COMPUTER SYSTEM TIMING SPECIFICATIONS; FLIP FLOP MACHINE; LATCH MACHINE;

COMPUTER SYSTEMS, DIGITAL;

EID: 0024091371     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.7979     Document Type: Article

References (16)

1. Bakoglu, H.B., J.T. Walker, and J.D. Meindl, “A Symmetric Clock Distribution Tree and Optimized Highspeed Interconnections for Reduced Clock Skew in ULSI and WSI Circuits”, Proc. IEEE Intl Conf. on Computer Design, 1986.
2. Domenik, S., “OnChip Clock Buffers”, Lambda, 1st qtr., 1981.
3. Friedman, E., and S. Powell, “Design and Analysis of a Hierarchical Clock Distribution System for Synchronous Standard Cell/Macro-cell VLSI, IEEE J. Solid-State Circuits, Vol. SC-21, No. 2, 1986.
4. Glasser, L., and D. Dobberpuhl, The Design and Analysis of VLSI Circuits, chapt. 6, Addison-Wesley, Reading, Mass., 1985.
5. Hitchcock, R., Sr., Timing Verification and the Timing Analysis Program”, Proc. Design Automation Conf., 1982.
6. IBM 3033 Processor Complex TO/DM, IBM Corp., Mechanicsburg, Pa., 1981.
7. Kogge, P., “Hardware Design and Stage Cascading”, The Architecture of Pipelined Computers, chapt. 2, McGraw-Hill, New York, 1981.
8. Langdon, G., Jr., Computer Design, appendices C and D, Computeach Press, 1982.
9. Lob, C., and A. Elkins, “HP-9000: 18-Mhz Clock Distribution System”, HP J.,Aug. 1983.
10. Maini, J., J. McDonald, and L. Spangler, “A Clock Distribution Circuit with a 100-ps Skew Window”, Proc. Bipolar Circuits and Technology Meeting, 1987.
11. McCluskey, E.J., Logic Design Principles: With Emphasis on Testable Semicustom Circuits, chapts. 7-8, Prentice-Hall, Englewood Cliffs, N.J., 1986.
12. Seitz, C., “System Timing”, Introduction to VLSI Systems, chapt. 7, C. Mead and L. Conway, eds., Addison-Wesley, Reading, Mass., 1980.
13. Shoji, M., “Electrical Design of the BELLMAC-32A Microprocessor”, Proc. Circuits and Computers Conf., 1982.
14. Shoji, M., “Elimination of Process-Dependent Clock Skew in CMOS VLSI”, IEEE J.Solid-State Circuits, Vol. SC-21, No. 5, 1986.
15. Unger, S., and C.J. Tan, “Clocking Schemes for Highspeed Digital Systems,”IEEE Trans. Computers, Vol. C-35, No. 10, 1986.
16. Wagner, K.D., A Survey of Clock Distribution Techniques in Highspeed Computer Systems, tech. rpt. 86-309, CSL Stanford Electronics Lab., CRC 86-20, Stanford Univ., Stanford, Calif., 1986.